Team A4: Fmpga

This week, I updated the fixed point units/wrote a fixed point inverter, envelope generator, and applicators all in SystemVerilog, and verified all of their functionality against software models. The envelope generator currently has a bug that I believe I have narrowed down to an issue with multiplication, but I had to move on from it temporarily in order to finish out the rest of my parts before the presentation. I have integrated all of these parts into the larger APU…

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This week, I implemented and verified the software distortion effect. It uses entirely modular fixed point data types and is true to the hardware. In the picture below, the orange triangle wave is the input sound wave, and the blue curve is the output after applying the distortion effect. Demos came up a bit fast on me, so I decided to start integration before implementing the low/high pass filters. I addressed all Git reviews from Eric and Manav for all…

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This week, I finished the applicator model and its testbench. I spent too long trying to fiddle with parameterization, both within the testbench and model, since there will be multiple applicators that are all slightly different. In the end, I decided the best use of my time was to make a general applicator to show proof of concept, and worry about verifying each individual one once I implement the hardware. I don’t anticipate them being too different, so this shouldn’t…

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This week, I didn’t get much done unfortunately. I started work on the applicator  applicator software model, and the test bench is on its way but it’s a bit tricky to write because I need to emulate the  functionality of all the modulation sources (envelopes, LFOs, wavetables) in SystemVerilog, which isn’t trivial. It might be better to just test this module alone, without the software model. Next week, I really need to figure out what I’m doing with the applicator…

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This week, I implemented the wavetable oscillator in Python. It meets our requirements of <1% deviation in pitch, and can output sawtooth, square waves, and sine waves. I am very happy with it because it was the one component we were nervous about meeting our requirements for, since we didn’t have too much of a basis for deviation in pitch. The model was written very similar to how it would be implemented in hardware, so it should be fairly fast…

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This week, I implemented and verified a software model of the envelope detector module, which makes plots of like the image below for given values for attack, decay, sustain, and release. I’ve implemented it with hardware in mind, so it should be very easy to port it over to SystemVerilog. I’ve also worked on the software model for the wave table oscillator, which is proving to be more difficult than expected. I’ve put a lot of thought and testing into…

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This week, I worked on creating the test suite for our project. We decided that it was important to have software models to test against, and thought it was worth the time to create an automatic system to verify SystemVerilog output against a Python implementation of our modules. The test suite was completed and I am quite proud of how useful it is. Here is a subset of the files I created this week. Omitted is a template SystemVerilog +…

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