Browsed by
Author: jafinn

Product Pitch & Final Video

Product Pitch & Final Video

Comments 0 Comment

Digital synthesis is a convenient and powerful way to create and manipulate sounds. Software synthesizers run on a CPU are feature packed, but reliant on a slow and bulky general purpose computer. Hardware synthesizers are faster and more portable, but tend to provide limited control over the sound due to pricey ASICs and analog circuits. The FMPGA is a digital synthesizer built on an FPGA designed to bring software-level functionality to a high performance platform. Using a MIDI keyboard, a…

Read More Read More

Joe’s status report for 12/5

Joe’s status report for 12/5

Comments 0 Comment

This week, I updated the fixed point units/wrote a fixed point inverter, envelope generator, and applicators all in SystemVerilog, and verified all of their functionality against software models. The envelope generator currently has a bug that I believe I have narrowed down to an issue with multiplication, but I had to move on from it temporarily in order to finish out the rest of my parts before the presentation. I have integrated all of these parts into the larger APU…

Read More Read More

Joe’s status report for 11/21

Joe’s status report for 11/21

Comments 0 Comment

This week, I implemented the hardware description of the wavetable oscillator. To do so, this also required implementing ROM and the fixed-point unit in hardware. All of these transitions went quite smoothly, and the wavetable oscillator has been verified against my software model and they produce identical outputs over hundreds of thousands of clock cycles. I am starting to dip into expected slack weeks this week, but I plan to hopefully get a lot more of the hardware description completed…

Read More Read More

Team status report for 11/14

Team status report for 11/14

Comments 0 Comment

This week, we worked hard to get each of our respective components into something demo-able. Eric was able to show a software simulation of the display. Manav has the entire MIDI layer SystemVerilog code debugged in simulation and was working on transferring it to the FPGA. While he wasn’t able to get this done by the demo, he made a lot of headway learning about how to interface with the GPIO pins on the FPGA. Joe was able to write…

Read More Read More

Joe’s status report for 11/14

Joe’s status report for 11/14

Comments 0 Comment

Sorry this is late šŸ™ This week, I got a lot done. All of the code for integrating the APU has been written and mostly debugged. I also started writing the Wavetable oscillator, fixed point unit, and RAM in SystemVerilog. This is the current status for the APU integration: The software APU is able to modulate a signal using Wavetable oscillator and the LFOs. Theoretically, it would be able to use the envelope generators but they aren’t written in fixed…

Read More Read More

Team status update for 11/07

Team status update for 11/07

Comments 0 Comment

This week, we have all been working towards making working prototypes for the upcoming demos. Manav has been working on being able to show we can decode simulated MIDI inputs. The MIDI keyboard came in this week, so he is able to sample real inputs for testing, though this might not be feasible before the demo. Eric has finished the encoders module and is working on demoing our display. He won’t be able to demo the real LCD screen yet,…

Read More Read More

Joe’s status update for 11/07

Joe’s status update for 11/07

Comments 0 Comment

This week, I implemented and verified the software distortion effect. It uses entirely modular fixed point data types and is true to the hardware. In the picture below, the orange triangle wave is the input sound wave, and the blue curve is the output after applying the distortion effect. Demos came up a bit fast on me, so I decided to start integration before implementing the low/high pass filters. I addressed all Git reviews from Eric and Manav for all…

Read More Read More

Team status update for 10/31

Team status update for 10/31

Comments 0 Comment

Right now, Manav is in need of the MIDI keyboard to start accurately testing his module. We placed the order earlier this week, and hopefully it comes in soon. We’ve received the rest of our parts, so all other testing can start as soon as we’re ready. Aside from that, the only major roadblock right now is time. We all had a rough couple of weeks because of midterms, but the mid-semester set of tests are over, so hopefully we…

Read More Read More

Joe’s status update 10/31

Joe’s status update 10/31

Comments 0 Comment

This week, I finished the applicator model and its testbench. I spent too long trying to fiddle with parameterization, both within the testbench and model, since there will be multiple applicators that are all slightly different. In the end, I decided the best use of my time was to make a general applicator to show proof of concept, and worry about verifying each individual one once I implement the hardware. I don’t anticipate them being too different, so this shouldn’t…

Read More Read More

Joe Status Update 10/25

Joe Status Update 10/25

Comments 0 Comment

This week, I didn’t get much done unfortunately. I started work on the applicatorĀ  applicator software model, and the test bench is on its way but it’s a bit tricky to write because I need to emulate theĀ  functionality of all the modulation sources (envelopes, LFOs, wavetables) in SystemVerilog, which isn’t trivial. It might be better to just test this module alone, without the software model. Next week, I really need to figure out what I’m doing with the applicator…

Read More Read More