This week, we worked hard to get each of our respective components into something demo-able. Eric was able to show a software simulation of the display. Manav has the entire MIDI layer SystemVerilog code debugged in simulation and was working on transferring it to the FPGA. While he wasn’t able to get this done by the demo, he made a lot of headway learning about how to interface with the GPIO pins on the FPGA. Joe was able to write all the code to integrate the software into the completely APU. He has a bit of debugging left to do, but since the proof of concept is there, he has put it aside for now to work on hardware implementations.

Thanksgiving break came up on us quickly, so each of us has some work to do on the FPGA before someone takes it home. That might cause some logistical issues for us.