This week, I updated the fixed point units/wrote a fixed point inverter, envelope generator, and applicators all in SystemVerilog, and verified all of their functionality against software models. The envelope generator currently has a bug that I believe I have narrowed down to an issue with multiplication, but I had to move on from it temporarily in order to finish out the rest of my parts before the presentation. I have integrated all of these parts into the larger APU module, and am currently in the process of verifying it. At the moment, this is the completed state of the APU, however some of the interconnects are currently being verified:

Of course, I have dipped far into my slack time (as I should have expected). What remains to be done is the filter and distortion modules. I am unfortunately concerned that I won’t have time to finish the filter before the presentation. I have been and will continue to be working non-stop to complete the APU by tomorrow night. Luckily, I have built the APU in such a way that sub-components can be “plugged in” quite easily; this makes the entire design very modular, and so even if the filters cannot be completed, it will still be able to meet all other requirements.