Sorry this is late 🙁

This week, I got a lot done. All of the code for integrating the APU has been written and mostly debugged. I also started writing the Wavetable oscillator, fixed point unit, and RAM in SystemVerilog.

This is the current status for the APU integration:

The software APU is able to modulate a signal using Wavetable oscillator and the LFOs. Theoretically, it would be able to use the envelope generators but they aren’t written in fixed point. Completing this kept me on schedule and I was able to have a significant portion of my work done for the demo.

I think I am going to push off the filters until after I’m done implementing the rest of the hardware. I was originally supposed to have help from Eric, but his components are taking longer than anticipated and I need to get moving on working on the FPGA.