This week, I didn’t get much done unfortunately. I started work on the applicator  applicator software model, and the test bench is on its way but it’s a bit tricky to write because I need to emulate the  functionality of all the modulation sources (envelopes, LFOs, wavetables) in SystemVerilog, which isn’t trivial. It might be better to just test this module alone, without the software model.

Next week, I really need to figure out what I’m doing with the applicator and write the effects, or else I’ll be behind schedule.