This week, I worked on creating the test suite for our project. We decided that it was important to have software models to test against, and thought it was worth the time to create an automatic system to verify SystemVerilog output against a Python implementation of our modules. The test suite was completed and I am quite proud of how useful it is.

Here is a subset of the files I created this week. Omitted is a template SystemVerilog + Python test bench as well as a SystemVerilog utility module for capturing cycle data (not pictured because the folders on Git weren’t too interesting).

I also set up a Jira webpage to manage our progress and contributions to the project.

I am a bit behind schedule, due to the test environment taking a bit more work than anticipated as well as some assignments in other classes. By next week, I will have the software simulators of my first modules done and tested, so I can get to work writing SystemVerilog the week after. Then I will be back on schedule.