Post your reviews for the required readings in the paper review system.

• G. M. Amdahl, "Validity of the single processor approach to achieving large scale computing capabilities," AFIPS Conference, April 1967.
• G. E. Moore, "Cramming more components onto integrated circuits," Electronics, April 1965.
• Ronen et al., "Coming Challenges in Microarchitecture and Architecture," Proceedings of the IEEE, vol. 89, no. 11, 2001.
• Y. N. Patt, "Requirements, bottlenecks, and good fortune: agents for microprocessor evolution," Proceedings of the IEEE, vol. 89, no. 11, 2001.

• Colwell et al., "Instruction Sets and Beyond: Computers, Complexity, and Controversy," Computer, September 1985.

On-Chip Networks

• Dally et al., "Route Packets, Not Wires: On-Chip Interconnection Networks," DAC, June 2001.
• Wentzlaff et al., "On-Chip Interconnection Architecture of the Tile Processor," Micro, IEEE, November 2007.
• Grot et al., "Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-a-Chip," Micro, December 2009.

Main Memory Controllers

• Moscibroda et al., "Memory performance attacks: Denial of memory service in multi-core systems," Usenix Security Symposium, 2007.
• Rixner et al., "Memory Access Scheduling," ISCA, 2000.

Architecture Reference Manuals

• Digital Equipment Corp., “VAX11 780 Architecture Handbook,” 1977-78
• Intel Corp. “Intel 64 and IA-32 Architectures Software Developer’s Manual”

Compilers

• Wulf, "Compilers and Computer Architecture," IEEE Computer, 1981.

• Herlihy et al., "Transactional Memory: Architectural Support for Lock-free Data Structures," ISCA, 1993.

• , "Preliminary discussion of the logical design of an electronic computing instrument," Institute for Advanced Study , 1946.

• Burton Smith, "A pipelined, shared resource MIMD computer," ICPP 1978.
• Kirman et al., "On-Chip Optical Technology in Future Bus-Based Multicore Designs," IEEE Micro Top Picks 2007.

• Yiannakis Sazeides, James E. Smith: "The Predictability of Data Values," MICRO 1997: 248-258
• Mikko H. Lipasti, Christopher B. Wilkerson, John Paul Shen: "Value Locality and Load Value Prediction," ASPLOS 1996: 138-147

• Smith and Plezskun, “Implementing Precise Interrupts in Pipelined Processors,” IEEE Trans on Computers 1988 and ISCA 1985
• Smith and Sohi, "The Microarchitecture of Superscalar Processors," Proc IEEE 1995

• Hwu and Patt, "Checkpoint Repair for Out-of-order Execution Machines," ISCA 1987

• Jacob and Mudge, "Virtual Memory in Contemporary Microprocessors," IEEE Micro, vol. 18, no. 4, 1998

• Hennessy and Patterson, Sections 2.1-2.10 (inclusive)

• Stark, Brown, Patt, “On pipelining dynamic instruction scheduling logic,” MICRO 2000
• Boggs et al., “The microarchitecture of the Pentium 4 processor,” Intel Technology Journal, 2001
• Kessler, “The Alpha 21264 microprocessor,” IEEE Micro, March-April 1999
• Yeager, “The MIPS R10000 Superscalar Microprocessor,” IEEE Micro, April 1996

• Patt, Hwu, Shebanow, “HPS, a new microarchitecture: rationale and introduction,” MICRO 1985
• Patt et al., “Critical issues regarding HPS, a high performance microarchitecture,” MICRO 1985
• Anderson, Sparacio, Tomasulo, “The IBM System/360 Model 91: Machine Philosophy and Instruction Handling,” IBM Journal of R&D, Jan. 1967
• Tomasulo, “An Efficient Algorithm for Exploiting Multiple Arithmetic Units,” IBM Journal of R&D, Jan. 1967

• Jouppi, “Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers,” ISCA 1990
• Qureshi et al., “A Case for MLP-Aware Cache Replacement,“ ISCA 2006
• Wilkes, “Slave Memories and Dynamic Storage Allocation,” IEEE Trans. On Electronic Computers, 1965

• Mutlu et al., "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors," HPCA 2003
• Zhou, Dual-Core Execution: "Building a Highly Scalable Single-Thread Instruction Window," PACT 2005
• Mutlu et al., "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance," IEEE Micro Top Picks 2006

• Chrysos and Emer, "Memory Dependence Prediction Using Store Sets," ISCA 1998

• Hennessy and Patterson, Appendix C.1-C.3
• Jouppi, “Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers,” ISCA 1990
• Qureshi et al., “A Case for MLP-Aware Cache Replacement,“ ISCA 2006

• Seznec, "A Case for Two-way Skewed Associative Caches," ISCA 1993
• Chilimbi et al., "Cache-conscious Structure Definition," PLDI 1999
• Chilimbi et al., "Cache-conscious Structure Layout," PLDI 1999

• Pai et al., "Code Transformations to Improve Memory Parallelism," MICRO 1999

• Juan et al., "Data Caches for Superscalar Processors," ICS 1997

• Joseph and Grunwald, "Prefetching using Markov Predictors,' ISCA 1997

• Mowry et al., "Design and Evaluation of a Compiler Algorithm for Prefetching," ASPLOS 1992
• Srinath et al., "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers", HPCA 2007
• Mutlu et al., "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors," HPCA 2003

Same as previous lecture

• Cooksey et al., "A stateless, content-directed data prefetching mechanism," ASPLOS 2002
• Ebrahimi et al., "Techniques for Bandwidth-Efficient Prefetching of Linked Data Structures in Hybrid Prefetching Systems," HPCA 2009
• Luk, "Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors," ISCA 2001

• Moscibroda and Mutlu, "A Case for Bufferless Routing in On-Chip Networks", ISCA 2009
• Das et al., "Application-Aware Prioritization Mechanism for On-Chip Networks", MICRO 2009
• Das et al. "Aergia: Exploiting Packet-Latency Slack in On-Chip Networks", ISCA 2010
• Nychis et al., "Next Generation On-Chip Networks: What Kind of Congestion Control do we Need?", Hotnets 2010

• Ebrahimi et al., "Coordinated Management of Multiple Prefetchers in Multi-Core Systems," MICRO 2009

• Qureshi and Patt, "Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches," MICRO 2006

• Lin et al., "Gaining Insights into Multi-Core Cache Partitioning:Bridging the Gap between Simulation and Real Systems," HPCA 2008
• Qureshi et al., "Adaptive Insertion Policies for High-Performance Caching," ISCA 2007

• Mutlu and Moscibroda, "Parallelism-Aware Batch Scheduling:Enabling High-Performance and Fair Memory Controllers," IEEE Micro Top Picks 2009
• Mutlu and Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors," MICRO 2007

• Zhang et al., "A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality," MICRO 2000
• Lee et al., "Prefetch-Aware DRAM Controllers," MICRO 2008
• Rixner et al., "Memory Access Scheduling," ISCA 2000

Same as previous lecture

• Patel et al., "Evaluation of design options for the trace cache fetch mechanism," IEEE TC 1999
• Palacharla et al., "Complexity Effective Superscalar Processors," ISCA 1997

• Smith and Sohi, "The Microarchitecture of Superscalar Processors," Proc IEEE 1995
• Stark, Brown, Patt, "On pipelining dynamic instruction scheduling logic," MICRO 2000
• Boggs et al., "The microarchitecture of the Pentium 4 processor," Intel Technology Journal, 2001
• Kessler, "The Alpha 21264 microprocessor," IEEE Micro, March-April 1999

• Rotenberg et al., "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching," MICRO 1996

Same as previous lecture

Same as previous lecture

Same as previous lecture

• McFarling, "Combining Branch Predictors," DEC WRL TR, 1993
• Carmean and Sprangle, "Increasing Processor Performance by Implementing Deeper Pipelines," ISCA 2002

• Evers et al., "An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work," ISCA 1998
• Yeh and Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," ISCA 1992
• Jouppi and Wall, "Available instruction-level parallelism for superscalar and superpipelined machines," ASPLOS 1989
• Kim et al., "Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths," MICRO 2006
• Jimenez and Lin, "Dynamic Branch Prediction with Perceptrons," HPCA 2001

Same as previous lecture

• Kim et al., "Wish Branches: Enabling Adaptive and Aggressive Predicated Execution," IEEE Micro Top Picks, Jan/Feb 2006
• Kim et al., "Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication," IEEE Micro Top Picks, Jan/Feb 2007

• Fisher, "Very Long Instruction Word architectures and the ELI-512," ISCA 1983
• Huck et al., "Introducing the IA-64 Architecture," IEEE Micro 2000

• Russell, "The CRAY-1 computer system," CACM 1978
• Rau and Fisher, "Instruction-level parallel processing: history,overview, and perspective," Journal of Supercomputing, 1993
• Faraboschi et al., "Instruction Scheduling for Instruction Level Parallel Processors," Proc. IEEE, Nov. 2001

Same as previous lecture (Alternative Approaches to Concurrency)

• Lindholm et al., "NVIDIA Tesla: A Unified Graphics and Computing Architecture," IEEE Micro 2008
• Russell, "The CRAY-1 computer system," CACM 1978

• Fung et al., "Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow," MICRO 2007
• Luk et al., "Qilin: Exploiting Parallelism on Heterogeneous Multiprocessors with Adaptive Mapping," MICRO 2009