This week, we worked on catching up from the missed time last week. We all are well into designing our respective components. Currently, we don’t have any major risks for the project; we’ve spent a lot of time discussing the oscillator module, because it has turned out to be more complicated than we have planned for.
This week, I implemented and verified a software model of the envelope detector module, which makes plots of like the image below for given values for attack, decay, sustain, and release. I’ve implemented it with hardware in mind, so it should be very easy to port it over to SystemVerilog. I’ve also worked on the software model for the wave table oscillator, which is proving to be more difficult than expected. I’ve put a lot of thought and testing into…
This week, our team was spread pretty thin across lots of outside priorities. As a result, we are somewhat behind schedule. However, we did plan our project with the mindset that we would dedicate more and more time as the semester goes on, so the first week of our schedule was intentionally easy to account for an issue like this. As a result, we feel we shouldn’t have a problem making up the time next week. We looked through our…
This week, I mostly focused on determining how I would go about developing a software simulator for midi simulator utilizing the test suite that Joe ended up creating in python. In addition to this, I also spent a considerable time studying and creating a mock version of the MIDI decoder in SystemVerilog. The sampler is still something I have to study and understand so I can properly take in input from the MIDI at a consistent clock rate. Starting next…
This week, I worked on creating the test suite for our project. We decided that it was important to have software models to test against, and thought it was worth the time to create an automatic system to verify SystemVerilog output against a Python implementation of our modules. The test suite was completed and I am quite proud of how useful it is. Here is a subset of the files I created this week. Omitted is a template SystemVerilog +…
This week, I worked pretty heavily on the logistics and environment for the project. While Joe worked on testing environment, I did some work with my own setup, dealing with the style guide for the project as well as etiquette for pull requests. I finished reviewing Joe’s code, and now that the test environment is mostly finalized, I’m not as wary of jumping into writing my testbenches. I think I didn’t really get as much done as I wanted to,…