• P&P stands for Patt & Patel's Introduction to Computing Systems: From Bits and Gates to C and Beyond
  • (CMU WebISO) P&P Chapter 1 (Fundamentals)
  • (CMU WebISO) P&P Chapter 4 (The von Neumann Model)
  • (CMU WebISO) P&P Appendix A (The LC-3b ISA)
  • (CMU WebISO) P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)
• P&H stands for Patterson & Hennessy's Computer Organization and Design: The Hardware/Software Interface

• Lecture slides: pdf Slides ppt
• Example reviews on “Main Memory Scaling: Challenges and Solution Directions” (link to the paper)
  • Review 1
  • Review 2
• Example review on “Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems” (link to the paper)
  • Review 1

Required:

• For HW1: Patt, Y. (2001). Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE.

Mentioned during lecture:

• Hamming, R. W. (1950). Error Detecting and Error Correcting Codes. Bell System Technical Journal, 29(2).
• Hamming, R. W. (1986). You and Your Research. Transcription of the Bell Communications Research Colloquium Seminar.
  • youtube
• Rixner, S., Dally, W. J., Kapasi, U. J., Mattson, P., & Owens, J. D. (2000). Memory access scheduling. Proceedings of the 27th annual international symposium on Computer architecture.
• Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.
• Onur Mutlu and Thomas Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.
• Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda, "Reducing Memory Interference in Multicore Systems via Application-Aware * Memory Channel Partitioning", MICRO 2011.
• Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012.
• Onur Mutlu, "Memory Scaling: A Systems Architecture Perspective" Technical talk at MemCon 2013 (MEMCON), Santa Clara, CA, August 2013.
• Kevin Chang, Donghyuk Lee, Zeshan Chishti, Alaa Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu, "Improving DRAM Performance by Parallelizing Refreshes with Accesses", In HPCA 2014, Orlando, Feb. 2014.
• Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors", In ISCA-41, 2014.

Required:

• Patt, Y. (2001). Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE.
• Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.
• (CMU WebISO) P&P Chapter 1 (Fundamentals)
• P&H Chapters 1 and 2 (Intro, Abstractions, ISA, MIPS)

Mentioned during lecture:

Required:

• Note that you should familiarize yourself with these manuals. Please briefly skim through these manuals as you will probably need to refer to them while working on labs and homework
• MIPS Architecture Reference Manual
  • Manual (the instruction set reference starts on pg.469)
• Intel® 64 and IA-32 Architectures Software Developer Manual (2013)
  • (15MB) Combined Volumes 1-33

Mentioned during lecture:

• Klaiber, "The Technology Behind CrusoeTM Processors", Transmeta White Paper, 2000

Required:

• (CMU WebISO) P&P Chapter 4 (The von Neumann Model)
• (CMU WebISO) P&P Appendix A (The LC-3b ISA)
• (CMU WebISO) P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)

Mentioned during lecture:

Required

• None

Required:

• (CMU WebISO) P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)
• P&H Appendix D (Mapping Control to Hardware)

Optional:

• Wilkes, M. V. (1951). The best way to design an automatic calculating machine. Manchester University Computer Inaugural Conference.

Mentioned during lecture:

Required:

• None

Mentioned during lecture:

• Wilkes, M. V. (1951). The best way to design an automatic calculating machine. Manchester University Computer Inaugural Conference.
• Butler W. Lampson, “Hints for Computer System Design,” ACM Operating Systems Review, 1983.

Required:

• P&H Sections 4.9-4.11
• Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.
• Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.
• Mcfarling, S. (1993). Combining branch predictors. WRL Technical Note TN-36.
• Kessler, R. E. (1999). The Alpha 21264 Microprocessor. IEEE Micro.

Mentioned during lecture:

• Pettis, K., & Hansen, R. C. (1990). Profile guided code positioning. Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation.

Required:

• P&H Sections 4.9-4.11
• Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.
• Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.
• Mcfarling, S. (1993). Combining branch predictors. WRL Technical Note TN-36.
• Kessler, R. E. (1999). The Alpha 21264 Microprocessor. IEEE Micro.

Mentioned during lecture:

• Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, and Onur Mutlu, Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery, HPCA 2015.
• Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, and Onur Mutlu, Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case, HPCA 2015.
• Gennady Pekhimenko, Tyler Huberty, Rui Cai, Onur Mutlu, Phillip P. Gibbons, Michael A. Kozuch, and Todd C. Mowry, Exploiting Compressed Block Size as an Indicator of Future Reuse, HPCA 2015.

Required:

• P&H Sections 4.9-4.11
• Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.
• Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.
• Mcfarling, S. (1993). Combining branch predictors. WRL Technical Note TN-36.
• Kessler, R. E. (1999). The Alpha 21264 Microprocessor. IEEE Micro.

Mentioned in the Lecture:

• Ball, T., & Larus, J. R. (1993). Branch prediction for free. Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation.
• Smith, J. E. (1981). A study of branch prediction strategies. Proceedings of the 8th annual symposium on Computer Architecture.
• Yeh, T.-Y., & Patt, Y. N. (1991). Two-level adaptive training branch prediction. Proceedings of the 24th annual international symposium on Microarchitecture.
• Chang, P.-Y., Hao, E., Yeh, T.-Y., & Patt, Y. (1994). Branch classification: a new mechanism for improving branch predictor performance. Proceedings of the 27th annual international symposium on Microarchitecture.
• Daniel A. Jimenez and Calvin Lin. 2001. Dynamic Branch Prediction with Perceptrons. In Proceedings of the 7th International Symposium on High-Performance Computer Architecture (HPCA '01)
• E. M. Riseman and C. C. Foster. 1972. The Inhibition of Potential Parallelism by Conditional Jumps. IEEE Trans. Comput. 21, 12 (December 1972)
• Po-Yung Chang, Eric Hao, and Yale N. Patt. 1997. Target prediction for indirect jumps. ISCA'97.
• Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, and Robert Cohn. 2007. VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. ISCA'07