• P&P stands for Patt & Patel's Introduction to Computing Systems: From Bits and Gates to C and Beyond
  • (CMU WebISO) P&P Chapter 1 (Fundamentals)
  • (CMU WebISO) P&P Chapter 4 (The von Neumann Model)
  • (CMU WebISO) P&P Appendix A (The LC-3b ISA)
  • (CMU WebISO) P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)
• P&H stands for Patterson & Hennessy's Computer Organization and Design: The Hardware/Software Interface

• Lecture slides: pdf Slides ppt
• Example reviews on “Main Memory Scaling: Challenges and Solution Directions” (link to the paper)
  • Review 1
  • Review 2
• Example review on “Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems” (link to the paper)
  • Review 1

Required:

• For HW1: Patt, Y. (2001). Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE.

Mentioned during lecture:

• Hamming, R. W. (1950). Error Detecting and Error Correcting Codes. Bell System Technical Journal, 29(2).
• Hamming, R. W. (1986). You and Your Research. Transcription of the Bell Communications Research Colloquium Seminar.
  • youtube
• Rixner, S., Dally, W. J., Kapasi, U. J., Mattson, P., & Owens, J. D. (2000). Memory access scheduling. Proceedings of the 27th annual international symposium on Computer architecture.
• Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.
• Onur Mutlu and Thomas Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.
• Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda, "Reducing Memory Interference in Multicore Systems via Application-Aware * Memory Channel Partitioning", MICRO 2011.
• Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012.
• Onur Mutlu, "Memory Scaling: A Systems Architecture Perspective" Technical talk at MemCon 2013 (MEMCON), Santa Clara, CA, August 2013.
• Kevin Chang, Donghyuk Lee, Zeshan Chishti, Alaa Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu, "Improving DRAM Performance by Parallelizing Refreshes with Accesses", In HPCA 2014, Orlando, Feb. 2014.
• Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors", In ISCA-41, 2014.

Required:

• Patt, Y. (2001). Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE.
• Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.
• (CMU WebISO) P&P Chapter 1 (Fundamentals)
• P&H Chapters 1 and 2 (Intro, Abstractions, ISA, MIPS)

Mentioned during lecture:

Required:

• Note that you should familiarize yourself with these manuals. Please briefly skim through these manuals as you will probably need to refer to them while working on labs and homework
• MIPS Architecture Reference Manual
  • Manual (the instruction set reference starts on pg.469)
• Intel® 64 and IA-32 Architectures Software Developer Manual (2013)
  • (15MB) Combined Volumes 1-33

Mentioned during lecture:

• Klaiber, "The Technology Behind CrusoeTM Processors", Transmeta White Paper, 2000

Required:

• (CMU WebISO) P&P Chapter 4 (The von Neumann Model)
• (CMU WebISO) P&P Appendix A (The LC-3b ISA)
• (CMU WebISO) P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)

Mentioned during lecture:

Required

• None

Required:

• (CMU WebISO) P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)
• P&H Appendix D (Mapping Control to Hardware)

Optional:

• Wilkes, M. V. (1951). The best way to design an automatic calculating machine. Manchester University Computer Inaugural Conference.

Mentioned during lecture:

Required:

• None

Mentioned during lecture:

• Wilkes, M. V. (1951). The best way to design an automatic calculating machine. Manchester University Computer Inaugural Conference.
• Butler W. Lampson, “Hints for Computer System Design,” ACM Operating Systems Review, 1983.

Required:

• P&H Sections 4.9-4.11
• Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.
• Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.
• Mcfarling, S. (1993). Combining branch predictors. WRL Technical Note TN-36.
• Kessler, R. E. (1999). The Alpha 21264 Microprocessor. IEEE Micro.

Mentioned during lecture:

• Pettis, K., & Hansen, R. C. (1990). Profile guided code positioning. Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation.

Required:

• P&H Sections 4.9-4.11
• Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.
• Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.
• Mcfarling, S. (1993). Combining branch predictors. WRL Technical Note TN-36.
• Kessler, R. E. (1999). The Alpha 21264 Microprocessor. IEEE Micro.

Mentioned during lecture:

• Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, and Onur Mutlu, Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery, HPCA 2015.
• Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, and Onur Mutlu, Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case, HPCA 2015.
• Gennady Pekhimenko, Tyler Huberty, Rui Cai, Onur Mutlu, Phillip P. Gibbons, Michael A. Kozuch, and Todd C. Mowry, Exploiting Compressed Block Size as an Indicator of Future Reuse, HPCA 2015.

Required:

• P&H Sections 4.9-4.11
• Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.
• Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.
• Mcfarling, S. (1993). Combining branch predictors. WRL Technical Note TN-36.
• Kessler, R. E. (1999). The Alpha 21264 Microprocessor. IEEE Micro.

Mentioned in the Lecture:

• Ball, T., & Larus, J. R. (1993). Branch prediction for free. Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation.
• Smith, J. E. (1981). A study of branch prediction strategies. Proceedings of the 8th annual symposium on Computer Architecture.
• Yeh, T.-Y., & Patt, Y. N. (1991). Two-level adaptive training branch prediction. Proceedings of the 24th annual international symposium on Microarchitecture.
• Chang, P.-Y., Hao, E., Yeh, T.-Y., & Patt, Y. (1994). Branch classification: a new mechanism for improving branch predictor performance. Proceedings of the 27th annual international symposium on Microarchitecture.
• Daniel A. Jimenez and Calvin Lin. 2001. Dynamic Branch Prediction with Perceptrons. In Proceedings of the 7th International Symposium on High-Performance Computer Architecture (HPCA '01)
• E. M. Riseman and C. C. Foster. 1972. The Inhibition of Potential Parallelism by Conditional Jumps. IEEE Trans. Comput. 21, 12 (December 1972)
• Po-Yung Chang, Eric Hao, and Yale N. Patt. 1997. Target prediction for indirect jumps. ISCA'97.
• Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, and Robert Cohn. 2007. VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. ISCA'07

Required:

Mentioned in the Lecture:

• Hwu and Patt (1987). Checkpoint Repair for Out-of-order Execution Machines.
• Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.
• Seznec (2005). Analysis of the O-GEometric History Length Branch Predictor. ISCA
• Daniel A. Jimenez and Calvin Lin. 2001. Dynamic Branch Prediction with Perceptrons. In Proceedings of the 7th International Symposium on High-Performance Computer Architecture (HPCA '01)

Required:

• Kessler, R. E. (1999). The Alpha 21264 Microprocessor. IEEE Micro.

Required:

• Kessler, R. E. (1999). The Alpha 21264 Microprocessor. IEEE Micro.
• Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.
• Lindholm, E., Nickolls, J., Oberman, S., & Montrym, J. (2008). NVIDIA Tesla: A Unified Graphics and Computing Architecture. Micro, IEEE.
• Fatahalian, K., & Houston, M. (2008). A closer look at GPUs. Commun. ACM.

Required

• Lindholm, E., Nickolls, J., Oberman, S., & Montrym, J. (2008). NVIDIA Tesla: A Unified Graphics and Computing Architecture. Micro, IEEE.
• Fatahalian, K., & Houston, M. (2008). A closer look at GPUs. Commun. ACM.

Mentioned during lecture:

• Fung, W. W. L., Sham, I., Yuan, G., & Aamodt, T. M. (2007). Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture.
• Suleman, M. A., Mutlu, O., Qureshi, M. K., & Patt, Y. N. (2009). Accelerating critical section execution with asymmetric multi-core architectures. Proceedings of the 14th international conference on Architectural support for programming languages and operating systems.
• Flynn, M. J. (1966). Very high-speed computing systems. Proceedings of the IEEE.
• Fisher, J. A. (1983). Very Long Instruction Word architectures and the ELI-512. Proceedings of the 10th annual international symposium on Computer architecture.
• Smith, J. E. (1982). Decoupled access/execute computer architectures. Proceedings of the 9th annual symposium on Computer Architecture.
• Smith, J. E. (1984). Decoupled access/execute computer architectures. ACM Trans. Comput. Syst.
• Smith, J. E., Dermer, G. E., Vanderwarn, B. D., Klinger, S. D., & Rozewski, C. M. (1987). The ZS-1 central processor. Proceedings of the second international conference on Architectual support for programming languages and operating systems.
• Smith, J. E. (1989). Dynamic instruction scheduling and the Astronautics ZS-1. IEEE Computer.
• Kung, H. T. (1982). Why Systolic Architectures? IEEE Computer.
• Annaratone, M., Arnould, E., Gross, T., Kung, H. T., & Lam, M. S. (1986). Warp architecture and implementation. Proceedings of the 13th annual international symposium on Computer architecture.
• Annaratone, M., Arnould, E., Gross, T., Kung, H. T., & Lam, M. (1987). The warp computer: Architecture, implementation, and performance. IEEE Transactions on Computers.

Required

• Lindholm, E., Nickolls, J., Oberman, S., & Montrym, J. (2008). NVIDIA Tesla: A Unified Graphics and Computing Architecture. Micro, IEEE.
• Fatahalian, K., & Houston, M. (2008). A closer look at GPUs. Commun. ACM.

Mentioned during lecture:

• Fung, W. W. L., Sham, I., Yuan, G., & Aamodt, T. M. (2007). Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture.
• Fisher, J. A. (1983). Very Long Instruction Word architectures and the ELI-512. Proceedings of the 10th annual international symposium on Computer architecture.
• Smith, J. E. (1982). Decoupled access/execute computer architectures. Proceedings of the 9th annual symposium on Computer Architecture.
• Smith, J. E. (1984). Decoupled access/execute computer architectures. ACM Trans. Comput. Syst.
• Smith, J. E., Dermer, G. E., Vanderwarn, B. D., Klinger, S. D., & Rozewski, C. M. (1987). The ZS-1 central processor. Proceedings of the second international conference on Architectual support for programming languages and operating systems.
• Smith, J. E. (1989). Dynamic instruction scheduling and the Astronautics ZS-1. IEEE Computer.
• Kung, H. T. (1982). Why Systolic Architectures? IEEE Computer.
• Annaratone, M., Arnould, E., Gross, T., Kung, H. T., & Lam, M. S. (1986). Warp architecture and implementation. Proceedings of the 13th annual international symposium on Computer architecture.
• Annaratone, M., Arnould, E., Gross, T., Kung, H. T., & Lam, M. (1987). The warp computer: Architecture, implementation, and performance. IEEE Transactions on Computers.
• Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar Iyer, and Chita R. Das. 2013. Orchestrated scheduling and prefetching for GPGPUs. ISCA '13
• Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, and Yale N. Patt. 2011. Improving GPU performance via large warps and two-level warp scheduling.MICRO-44

Mentioned during lecture:

• Subramanian et al., “MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,” HPCA 2013
• Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.
• Kung, H. T. (1982). Why Systolic Architectures? IEEE Computer.
• Fisher, J. A. (1981). Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Trans. Comput.
• Hwu, W.-M. W., Mahlke, S. A., Chen, W. Y., Chang, P. P., Warter, N. J., Bringmann, R. A., Ouellette, R. G., et al. (1993). The superblock: an effective technique for VLIW and superscalar compilation. J. Supercomput.
• Mahlke, S. A., Lin, D. C., Chen, W. Y., Hank, R. E., & Bringmann, R. A. (1992). Effective compiler support for predicated execution using the hyperblock. Proceedings of the 25th annual international symposium on Microarchitecture.
• Melvin, S., & Patt, Y. (1995). Enhancing instruction scheduling with a block-structured ISA. Int. J. Parallel Program.
• Hao, E., Chang, P.-Y., Evers, M., & Patt, Y. N. (1996). Increasing the instruction fetch rate via block-structured instruction set architectures. Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture.
• Huck, J., Morris, D., Ross, J., Knies, A., Mulder, H., & Zahir, R. (2000). Introducing the IA-64 architecture. IEEE Micro.
• Annaratone, M., Arnould, E., Gross, T., Kung, H. T., & Lam, M. S. (1986). Warp architecture and implementation. Proceedings of the 13th annual international symposium on Computer architecture.
• Annaratone, M., Arnould, E., Gross, T., Kung, H. T., & Lam, M. (1987). The warp computer: Architecture, implementation, and performance. IEEE Transactions on Computers.
• Fisher, J. A. (1983). Very Long Instruction Word architectures and the ELI-512. Proceedings of the 10th annual international symposium on Computer architecture.
• Smith, J. E. (1982). Decoupled access/execute computer architectures. Proceedings of the 9th annual symposium on Computer Architecture.
• Smith, J. E. (1984). Decoupled access/execute computer architectures. ACM Trans. Comput. Syst.
• Rau and Fisher, “Instruction-level parallel processing: history, overview, and perspective,” Journal of Supercomputing, 1993.
• Faraboschi et al., “Instruction Scheduling for Instruction Level Parallel Processors,” Proc. IEEE, Nov. 2001.

Required:

• Huck, J., Morris, D., Ross, J., Knies, A., Mulder, H., & Zahir, R. (2000). Introducing the IA-64 architecture. IEEE Micro.
• P&H Chapters 5.1-5.3 (cache chapters)
• Hamacher et al. Chapters 8.1-8.7 (cache/memory chapters)
• Wilkes, M. V. (1965). Slave Memories and Dynamic Storage Allocation. IEEE Transactions on Electronic Computers.
• Liptay, “Structural aspects of the System/360 Model 85 II: the cache,” IBM Systems Journal, 1968.

Required:

• Wilkes, M. V. (1964). Slave Memories and Dynamic Storage Allocation. IEEE Transactions on Electronic Computers.
• nQureshi et al., “A Case for MLP-Aware Cache Replacement,“ ISCA 2006.
• P&H Chapters 5.1-5.3 (cache chapters)
• Hamacher et al. Chapters 8.1-8.7 (cache/memory chapters)

Mentioned During Lecture:

• qBelady, “A study of replacement algorithms for a virtual-storage computer,” IBM Systems Journal, 1966.

Required:

• Wilkes, M. V. (1964). Slave Memories and Dynamic Storage Allocation. IEEE Transactions on Electronic Computers.
• Qureshi et al., “A Case for MLP-Aware Cache Replacement,“ ISCA 2006.
• P&H Chapters 5.1-5.3 (cache chapters)
• Hamacher et al. Chapters 8.1-8.7 (cache/memory chapters)

Mentioned During Lecture:

• Jouppi, N. P. (1990). Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. Proceedings of the 17th annual international symposium on Computer Architecture.
• Mutlu, O., Stark, J., Wilkerson, C., & Patt, Y. N. (2003). Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. Proceedings of the 9th International Symposium on High-Performance Computer Architecture.
• Seznec. A Case for Two-Way Skewed-Associative Caches. ISCA 1993.
• Kroft. Lockup-Free Instruction Fetch/Prefetch Cache Organization. ISCA 1981.
• Qureshi and Patt. Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. MICRO 2006.
• Suh et al. A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. HPCA 2002.

Required:

• Section 5.4 in P&H

Mentioned During Lecture:

• Section 8.8 in Hamacher et al.
• Megiddo and Modha, “ARC: A Self-Tuning, Low Overhead Replacement Cache,” FAST 2003.

Required:

• Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,” HPCA 2013. (Sections 1 and 2)
• Kim et al., “A Case for Subarray-Level Parallelism (SALP) in DRAM,” ISCA 2012. (Sections 1 and 2)
• Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012. (Sections 1 and 2)
• Onur Mutlu, Justin Meza, and Lavanya Subramanian, "The Main Memory System: Challenges and Opportunities," Invited Article in Communications of the Korean Institute of Information Scientists and Engineers (KIISE), 2015.

Mentioned During Lecture:

• Kim+, “Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,” ISCA 2014.
• Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, and Onur Mutlu, "Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery," Proceedings of the 21st International Symposium on High-Performance Computer Architecture (HPCA), Bay Area, CA, February 2015.
• Kang+, "Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling"

Required:

• Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,” HPCA 2013. (Sections 1 and 2)
• Kim et al., “A Case for Subarray-Level Parallelism (SALP) in DRAM,” ISCA 2012. (Sections 1 and 2)
• Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012.
• Onur Mutlu, Justin Meza, and Lavanya Subramanian, "The Main Memory System: Challenges and Opportunities," Invited Article in Communications of the Korean Institute of Information Scientists and Engineers (KIISE), 2015.

Mentioned During Lecture:

• Moscibroda and Mutlu, “Memory performance attacks: Denial of memory service in multi-core systems,”USENIX Security 2007
• Onur Mutluand Thomas Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors" ISCA 2008
• Onur Mutlu and Thomas Moscibroda, "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM," ISCA 2008
• Yoongu Kim, Michael Papamichael, Onur Mutlu, and Mor Harchol-Balter, "Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior" 43rd International Symposium on Microarchitecture (MICRO), pages 65-76, Atlanta, GA, December 2010
• Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter, "ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers"

Required:

• Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,” HPCA 2013. (Sections 1 and 2)
• Kim et al., “A Case for Subarray-Level Parallelism (SALP) in DRAM,” ISCA 2012. (Sections 1 and 2)
• Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012.
• Onur Mutlu, Justin Meza, and Lavanya Subramanian, "The Main Memory System: Challenges and Opportunities," Invited Article in Communications of the Korean Institute of Information Scientists and Engineers (KIISE), 2015.

Mentioned During Lecture:

• Moscibroda and Mutlu, “Memory performance attacks: Denial of memory service in multi-core systems,”USENIX Security 2007
• Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda, "Reducing Memory Interference in Multicore Systems via Application-Awareness"
• Wang et al., “A-DRM: Architecture-aware Distributed Resource Management of Virtualized Clusters,” VEE 2015.
• Ebrahimi, E., Miftakhutdinov, R., Fallin, C., Lee, C. J., Joao, J. A., Mutlu, O., & Patt, Y. N. (2011). Parallel application memory scheduling. Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture.
• Ebrahimi, E., Lee, C. J., Mutlu, O., & Patt, Y. N. (2010). Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems.
• Bloom, “Space/Time Trade-offs in Hash Coding with Allowable Errors”, CACM 1970
• Liu et al., “An Experimental Study of Data Retention Behavior in Modern DRAM Devices,” ISCA 2013.
• Kevin Chang, Donghyuk Lee, Zeshan Chishti, Alaa Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu, "Improving DRAM Performance by Parallelizing Refreshes with Accesses", In HPCA 2014, Orlando, Feb. 2014.

Required:

• Mutlu et al., “Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors,” HPCA 2003.
• Srinathet al., “Feedback directed prefetching”, HPCA 2007.

Mentioned During Lecture:

• Kim et al., “Ramulator: A Fast and Extensible DRAM Simulator,” IEEE Computer Architecture Letters 2015.
• Seshadri et al., “The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing,”PACT 2012.
• Lee et al., “DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems,”HPS Technical Report, April 2010.
• Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,” HPCA 2013. (Sections 1 and 2)
• Kim et al., “A Case for Subarray-Level Parallelism (SALP) in DRAM,” ISCA 2012. (Sections 1 and 2)
• Ipek et al., “Self Optimizing Memory Controllers: A Reinforcement Learning Approach,”ISCA 2008
• Mutlu et al., "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance," ISCA 2005, IEEE Micro Top Picks 2006.
• Mutlu et al., "Address-Value Delta (AVD) Prediction," MICRO 2005.
• Armstrong et al., "Wrong Path Events," MICRO 2004.

Required:

• Onur Mutlu, Justin Meza, and Lavanya Subramanian, "The Main Memory System: Challenges and Opportunities," Invited Article in Communications of the Korean Institute of Information Scientists and Engineers (KIISE), 2015.

Mentioned During Lecture:

• Jouppi, “Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers,” ISCA 1990.
• Srinathet al., “Feedback directed prefetching”, HPCA 2007.

Required:

• Onur Mutlu, Justin Meza, and Lavanya Subramanian, "The Main Memory System: Challenges and Opportunities," Invited Article in Communications of the Korean Institute of Information Scientists and Engineers (KIISE), 2015.

Mentioned during lecture:

• Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012.
• Kim et al., “A Case for Exploiting Subarray-Level Parallelism in DRAM,” ISCA 2012.
• Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,” HPCA 2013.
• Liu et al., “An Experimental Study of Data Retention Behavior in Modern DRAM Devices,” ISCA 2013.
• Seshadri et al., “RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data,” MICRO 2013.
• Pekhimenko et al., “Linearly Compressed Pages: A Main Memory Compression Framework,” MICRO 2013.
• Chang et al., “Improving DRAM Performance by Parallelizing Refreshes with Accesses,” HPCA 2014.
• Khan et al., “The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study,” SIGMETRICS 2014.
• Luo et al., “Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost,” DSN 2014.
• Kim et al., “Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,” ISCA 2014.
• Meza et al., “Enabling Efficient and Scalable Hybrid Memories,” IEEE Comp. Arch. Letters 2012.
• Yoon et al., “Row Buffer Locality Aware Caching Policies for Hybrid Memories,” ICCD 2012.
• Kultursay et al., “Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative,” ISPASS 2013.
• Meza et al., “A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory,” WEED 2013.
• Lee et al. “Architecting Phase Change Memory as a Scalable DRAM Alternative,” ISCA 2009.
• Meza+, “Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field,” DSN 2015.
• Qureshi+, “AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems,” DSN 2015.
• Kim et al., “Ramulator: A Fast and Extensible DRAM Simulator,” IEEE Computer Architecture Letters 2015.
• Seshadri+, “The Dirty-Block Index,” ISCA 2014.
• Pekhimenko+, “Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches,” PACT 2012.
• Seshadri+, “The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing,” PACT 2012.
• Zhao+, “FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems,” MICRO 2014.
• Yoon, Meza+, “Efficient Data Mapping and Buffering Techniques for Multi-Level Cell Phase-Change Memories,” ACM TACO 2014.
• Gennady Pekhimenko, Tyler Huberty, Rui Cai, Onur Mutlu, Phillip P. Gibbons, Michael A. Kozuch, and Todd C. Mowry, Exploiting Compressed Block Size as an Indicator of Future Reuse, HPCA 2015.
• Lu+, “Loose Ordering Consistency for Persistent Memory,” ICCD 2014.
• Mutlu, O., Stark, J., Wilkerson, C., & Patt, Y. N. (2003). Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. Proceedings of the 9th International Symposium on High-Performance Computer Architecture.
• Cooksey et al., “A stateless, content-directed data prefetching mechanism,” ASPLOS 2002.
• Zilles and Sohi, “Execution-based Prediction Using Speculative Slices”, ISCA 2001.
• Zilles and Sohi, ”Understanding the backward slices of performance degrading instructions,” ISCA 2000.
• Frank Soltis,"Inside the AS/400"

Required:

• Amdahl, G. M. (1967). Validity of the single processor approach to achieving large scale computing capabilities. Proceedings of the April 18-20, 1967, spring joint computer conference.
• Lamport, L. (1979). How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs.
• (CMU WebISO) C&S, Chapters 5.1 & 5.3
• P&H, Chapter 5.8

Recommended:

• (CMU WebISO) Hill, Jouppi, Sohi. "Multiprocessors and Multicomputers," pp. 551-560 in Readings in Computer Architecture.
• (CMU WebISO) Hill, Jouppi, Sohi. "Dataflow and Multithreading," pp. 309-314 in Readings in Computer Architecture.
• Flynn, M. J. (1966). Very high-speed computing systems. Proceedings of the IEEE.
• Papamarcos, M. S., & Patel, J. H. (1984). A low-overhead coherence solution for multiprocessors with private cache memories. Proceedings of the 11th annual international symposium on Computer architecture.

Mentioned during lecture:

• Horner (1819). A new method of solving numerical equations of all orders, by continuous approximation. Philosophical Transactions of the Royal Society

Required:

• Lamport, L. (1979). How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs.
• Papamarcos, M. S., & Patel, J. H. (1984). A low-overhead coherence solution for multiprocessors with private cache memories. Proceedings of the 11th annual international symposium on Computer architecture.
• (CMU WebISO) C&S, Chapters 5.1 & 5.3
• P&H, Chapter 5.8

Recommended:

• Gharachorloo et al. (1990). Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors.
• Gharachorloo et al. (1991). Two Techniques to Enhance the Performance of Memory Consistency Models.
• Ceze et al. (2007). BulkSC: Bulk Enforcement of Sequential Consistency.
• Censier et al. (1978). A new solution to coherence problems in multicache systems.
• Goodman (1983). Using cache memory to reduce processor-memory traffic.
• Laudon et al. (1997). The SGI Origin: a ccNUMA highly scalable server.
• Martin et al. (2003). Token coherence: decoupling performance and correctness.
• Baer et al. (1988). On the inclusion properties for multi-level cache hierarchies.

Mentioned during lecture:

• (HTML) Dijkstra (1965) Cooperating Sequential Processes.

Required:

• (CMU WebISO) C&S, Chapters 5.1 & 5.3
• P&H, Chapter 5.8
• Papamarcos, M. S., & Patel, J. H. (1984). A low-overhead coherence solution for multiprocessors with private cache memories. Proceedings of the 11th annual international symposium on Computer architecture.

Recommended:

• Censier et al. (1978). A new solution to coherence problems in multicache systems.
• Goodman (1983). Using cache memory to reduce processor-memory traffic.
• Laudon et al. (1997). The SGI Origin: a ccNUMA highly scalable server.
• Martin et al. (2003). Token coherence: decoupling performance and correctness.
• Baer et al. (1988). On the inclusion properties for multi-level cache hierarchies.

Required:

• Seshadri et al., “RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data,” MICRO 2013.