Labs

Lab 1: Instruction Level MIPS Simulator (Due: Fri. 1/23)

Lab 1.5: SystemVerilog Warm-Up (Due: Never)

Lab 2: Single-Cycle MIPS (Due: Fri. 2/6)

Lab 3: Pipelined MIPS (Due: Fri. 2/20)

Lab 4: Branch Prediction (Due: Fri. 03/06)

Lab 5: Data Cache (Due: Sun. 03/22)

Lab 6: Simulating Caches and Branch Prediction (Due: Fri. 04/03)

Lab 7: Memory Hierarchy (Due: Fri. 04/17, but can submit until 5/1)

Lab 8: Multicore and Cache Coherence (Extra Credit)