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Shayaan’s Status Report 2/21

This week, after creating the presentation and finalizing the major design requirements, I began working on the SystemVerilog that will be implemented on the DE10 Standard. I completed the sine, square, triangle, and noise oscillators and visually verified their outputs using the waveform viewer. I also created basic testbenches for each oscillator to evaluate their waveforms at different tuning words (frequencies).

Since I had already developed the saw oscillator earlier, we now have a prototype oscillator for every waveform we intend to generate. At the moment, the oscillators output waveforms that are meant to be interpreted as two’s complement values, but I still need to check the CODEC specifications to confirm what format it expects. I also plan to determine the maximum frequency at which each waveform can operate and whether this limit differs among the oscillators.

In addition to these two tasks, the next steps are to create an oscillator adder that combines multiple waveforms and to develop a MATLAB script that performs the same function so we can compare the results through inspection. Once the overall algorithm is finalized, I will run more comprehensive tests.

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Shayaan’s Update 02/14

This week, I worked on finalizing the FPGA we will use as the main processing component of our digital synthesizer. We selected the DE10 because it includes 112 DSP blocks, a 50 MHz clock, audio I/O ports, and a 24-bit CODEC. We believe these features are sufficient to meet our design requirements.

I also created a more detailed block diagram that includes our four voices, the communication protocol with the PC, and the audio output pipeline. The diagram specifies the algorithms we plan to use for modules such as the sawtooth oscillator (phase accumulator) and the noise oscillator (LFSR).

Additionally, I began developing oscillator prototypes and successfully implemented a basic sawtooth waveform module that takes a frequency input and produces a 24-bit resolution output waveform. While developing this module, I learned how to view analog waveforms using VCS, which allows us to visualize how our signals change over time.

One public safety concern related to our project is excessive sound exposure. Prolonged exposure to sound levels above 85 dB can cause hearing damage. Therefore, if we include headphone peripherals, it is important to ensure that the output does not exceed safe listening thresholds.

Additional safety considerations include proper power regulation, adequate electrical insulation, and thermal management. Any components that could pose even a minor hazard should be properly enclosed or isolated from the user. By prioritizing these safety measures, we aim to ensure that our digital synthesizer remains safe and accessible to all users.

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Shayaan’s Update 02/07

This week we started flushing out our design more. We presented our proposal in class and now are finding parts that fit our specific needs. I am currently doing some research to find what FPGA is best for our application. The ECE capstone inventory has DE0-nano, Ultra 96-V2, Radiano CS-ULX3S-01, and DE10-Standard. I am still figuring out what specs are required for our use case, but we would like to have 1 USB port, one port to connect to external DAC, enough processing components to handle 4 voices, and enough memory to handle delay effect bottleneck. Preliminary calculations suggest we will need 50-100 DSP slices, 200 Mhz clock, and 500kb internal memory.