This week, after creating the presentation and finalizing the major design requirements, I began working on the SystemVerilog that will be implemented on the DE10 Standard. I completed the sine, square, triangle, and noise oscillators and visually verified their outputs using the waveform viewer. I also created basic testbenches for each oscillator to evaluate their waveforms at different tuning words (frequencies).
Since I had already developed the saw oscillator earlier, we now have a prototype oscillator for every waveform we intend to generate. At the moment, the oscillators output waveforms that are meant to be interpreted as two’s complement values, but I still need to check the CODEC specifications to confirm what format it expects. I also plan to determine the maximum frequency at which each waveform can operate and whether this limit differs among the oscillators.
In addition to these two tasks, the next steps are to create an oscillator adder that combines multiple waveforms and to develop a MATLAB script that performs the same function so we can compare the results through inspection. Once the overall algorithm is finalized, I will run more comprehensive tests.