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Jake’s Status Report 3/28

This week we spent some time in Quartus bringing up the device. We all raced to get a top module with working audio output, which Daniel figured out first.

I finished the envelope-generator, handling the edge cases. You’re now able to interrupt a release with another key-press, jumping to the beginning of the attack, which seemed initially unnecessary as I thought another voice would eliminate the need to handle this case. However, this logic handles another key being pressed whilst the bank of voices is all in use. Inside the bank we can have an arbitration that “evicts” a voice inside of the “retrigger window” while a note is being released. Whilst this case may not arise in the use of a portamento, our current implementation doesn’t have this feature. The net effect is that when more keys are pressed than are voices, and held down, the oldest are held. But any key which happens to be in release will be replaced.

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Team Status Report for 03/28

This week, the team has been trying to clean up the SystemVerilog HDL for the WaveShaper core and implement it on the FPGA to demonstrate what it can do.

Shayaan has been working on the filtering and regularizing the oscillators for making all the tones sound more similar. Jake has been adjusting the ADSR envelope, adding additional logic and safeguards to prevent glitching. Daniel has been working on setting up end-to-end I/O on the DE-10 Standard FPGA development board.

This coming week, we hope to have a scaffolding of the WaveShaper to then fill in during the month of April as the period to work on the project comes to a close.

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Daniel’s Status Report for 03/28

This week, I got audio output to work. Now, we have an easy-to-use streaming interface and can focus on the rest of the WaveShaper core. While it was mostly just pruning small errors in the protocol, it was fairly time consuming.

I have moved onto serial communications, attempting to get a structure up before the interim demo such that we can stream live music to show off the WaveShaper’s unique sound.

Progress is going slightly slower than I like, it has again been a bit of a struggle with an unfamiliar tool to bridge the HPS ARM-core with the FPGA fabric using AXI. Seeing as the deadline approaches, I am looking into using the Avalon-MM interface instead.

I am aiming to have an end-to-end music playing device by Sunday evening by integrating the SystemVerilog which we have so far been simulating on actual hardware.

This week, I also spent some time on a MIDI parsing state machine which is as of now just on paper.

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Shayaan’s Status Report 3/28

This week, we worked on synthesizing the oscillators on the FPGA to produce a real audio output signal. This required correctly driving the DAC and initializing I2C communication with it. Ultimately, we were successful in driving the DAC using our previously developed oscillators. However, we noticed some issues with the periodicity of certain waveforms, as well as with the sine wave lookup table (LUT).

While working on fixing the oscillators and synthesizing a filter onto the FPGA, I encountered an issue accessing my account on the HH machines. Whenever I try to log in, I am redirected back to the username page. This has prevented me from synthesizing additional modules on the FPGA and continuing my work.

The next steps are to determine why I cannot access my account on the HH machines and then resume synthesizing modules such as filters and envelopes so we can move on to implementing effects.

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Jake’s Status Report

This week I added a counter-based clock-divider to produce an audio clock from the onboard 50MHz main. This approach won’t be final, as we’ll need to generate the audio clock higher in the system-hierarchy when the entire project goes onto the FPGA, but it was an effective workaround this week. 

Testbenching the envelope generator is producing coherent shapes, but adjusting ADSR values while the “key-press” signal is active affects the way the current voice moves through the stages. I am not confident on what “correct behavior” looks like here, and will need to do some exploring to decide what the design should do when we do things like shorten the attack in the middle of a really long attack-phase gradually rising in.

The majority of time this week was spent with Daniel working on synthesis. We developed a top-module to wrap The Waveshaper System-Verilog thus far, and connected Intel IP blocks to initialize the Wolfson Codec and drive the DAC line-out.  However, somewhere in the path we’ve got a bug, which I believe pertains to the I2C used to set up the DAC, as we’re using IP blocks to do this now. 

Additional time was spent resolving Quartus environment issues, which delayed synthesis and debugging. The next steps are to address the I2C configuration issues I suspect are present, validate with audio out, and to resolve the ADSR tests.

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Daniel’s Status Update for 03/21

This week, I started my implementation of the driving HDL for the WaveShaper’s audio output with Jake. This involved reading the documentation and datasheets for several different IP blocks and most importantly filtering out which ones not to use.

 

By the end of the week, we were able to get a noisy signal coming out of the hardware in a manner that is distinct from both environment noise and the state when the hardware for driving the speaker is not initialized. While this is a far cry from the desired result, I feel confident that my SystemVerilog is directly driving the output signal, so it is merely a matter of detecting whichever bug or oversight is throwing a wrench in the works.

 

This also marked the beginnings of a top-level module which has kick-started the iterative design process of architecting the HDL and interconnecting the modules that we have thus far.

 

I was not able to attend last week’s lab session and aim to better touch base with my teammates in preparation for the interim demo on Monday.

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Team Status Report 3/21

This week the team continued to work on the SystemVerilog implementation and Matlab pipeline. We have successfully completed the oscillators, mixer, envelope, and filter modules in both SystemVerilog and Matlab, marking a major milestone in the core signal path development. With these components in place, our focus is now shifting toward implementing the full filter set and verifying the correctness and stability of the overall pipeline. On the Matlab side, only the effects stage remains to be integrated to complete the end-to-end model.

In parallel, we worked with Quartus to synthesize an online example project onto the Intel DE-10 FPGA, gaining familiarity with the toolchain and deployment process. We are still working on establishing communication between the HPS core and the programmable logic (PL) fabric. Additionally, we made initial attempts to produce audio output from the FPGA, though this is still a work in progress.

At this stage, achieving reliable audio output from the FPGA is one of our top priorities, as it is essential for validating the full signal chain in real hardware and ensuring real-time performance. We will continue focusing on debugging the audio interface and establishing a stable connection between the processing pipeline and the output hardware. In parallel, completing the Matlab pipeline is equally critical, as finalizing the effects stage will provide a full reference model for formal verification. This will allow us to systematically compare outputs between Matlab and SystemVerilog, ensuring correctness before full hardware deployment.

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Shayaan’s 3/21 Status Report

Unfortunately this week I was unable to make as much progress as I would have liked. This week I started to create the SystemVerilog Filter and MATLAB filter files for the simulator. The filter we have chosen is a second order infinite impulse response filter.

A second-order infinite impulse response (IIR) filter is a discrete-time filter defined by a difference equation that uses both past inputs and past outputs, allowing it to achieve complex frequency responses with only a few coefficients. It is the lowest-order filter capable of producing resonance, making it especially useful for shaping audio signals in digital synthesizers. It is computationally efficient and well-suited for real-time and hardware implementations, while still providing flexibility through tunable parameters such as cutoff frequency and Q factor.

Next week, I will use waveform analysis to verify the SystemVerilog implementation, integrate the filter with the other system modules, and connect the MATLAB code into the overall simulation pipeline

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Team Status Report for 3/14

This week, the team continued working on the core modules in Verilog, while also getting the FPGA ready for testing our implementation on hardware.  We’ve got a MIDI controller in the mail as well, which will be all we need to test that the signal propagates through the pipeline correctly.

Daniel began writing wrappers for the Quartus side of our design,  starting on getting the modules we already have to synthesize.  Shayaan began writing MATLAB tests, which will allow for a much faster checking of our work, by virtue of being able to play directly samples generated from MATLAB, without having to go to hardware. This way, we can ensure what we intend to design will sound the way we expect it to. Jake continued working on the ADSR envelope generator, fixing issues as they arose in a test-bench.

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Jake’s Status Report 3/14

This week I focused again on implementing the ADSR envelope generator in verilog. I fleshed out a parent bank module, which generates an envelope per-voice with a generate loop. Every voice receives a key-press signal, and its own set of input parameters. While conventional synthesizers do not usually employ a per-voice envelope, it may be interesting to see what this could allow from a sound-design perspective, and supporting it in verilog is straightforward. In our final design, it’s likely I’ll either bundle all the voice signals together and run them in parallel through one-instance, or have only one instance of ADSR  controls for all the generators. Either way, this parent-level bank will support sweeping over the number of voices in our final design.

I revised the internal logic with the output level, and scaled the user-option input level in respect to the output level, as well as compiled a testbench. I still need to vary the state-update to be a parameterizable division of the clock, but this should be a quick-fix I’ll do tomorrow.

In addition to RTL, I helped Daniel get started flashing the FPGA through Quartus. There were a few points of confusion mounting JTAG, and flashing the image, but we sorted it out after some reading, and flashed test programs ensuring our line-out, audio-codec, and other parts are working. We started together on the top-level module to flash the verilog written so far.