This week the team continued to work on the SystemVerilog implementation and Matlab pipeline. We have successfully completed the oscillators, mixer, envelope, and filter modules in both SystemVerilog and Matlab, marking a major milestone in the core signal path development. With these components in place, our focus is now shifting toward implementing the full filter set and verifying the correctness and stability of the overall pipeline. On the Matlab side, only the effects stage remains to be integrated to complete the end-to-end model.
In parallel, we worked with Quartus to synthesize an online example project onto the Intel DE-10 FPGA, gaining familiarity with the toolchain and deployment process. We are still working on establishing communication between the HPS core and the programmable logic (PL) fabric. Additionally, we made initial attempts to produce audio output from the FPGA, though this is still a work in progress.
At this stage, achieving reliable audio output from the FPGA is one of our top priorities, as it is essential for validating the full signal chain in real hardware and ensuring real-time performance. We will continue focusing on debugging the audio interface and establishing a stable connection between the processing pipeline and the output hardware. In parallel, completing the Matlab pipeline is equally critical, as finalizing the effects stage will provide a full reference model for formal verification. This will allow us to systematically compare outputs between Matlab and SystemVerilog, ensuring correctness before full hardware deployment.