This week, I worked on finalizing the FPGA we will use as the main processing component of our digital synthesizer. We selected the DE10 because it includes 112 DSP blocks, a 50 MHz clock, audio I/O ports, and a 24-bit CODEC. We believe these features are sufficient to meet our design requirements.
I also created a more detailed block diagram that includes our four voices, the communication protocol with the PC, and the audio output pipeline. The diagram specifies the algorithms we plan to use for modules such as the sawtooth oscillator (phase accumulator) and the noise oscillator (LFSR).
Additionally, I began developing oscillator prototypes and successfully implemented a basic sawtooth waveform module that takes a frequency input and produces a 24-bit resolution output waveform. While developing this module, I learned how to view analog waveforms using VCS, which allows us to visualize how our signals change over time.
One public safety concern related to our project is excessive sound exposure. Prolonged exposure to sound levels above 85 dB can cause hearing damage. Therefore, if we include headphone peripherals, it is important to ensure that the output does not exceed safe listening thresholds.
Additional safety considerations include proper power regulation, adequate electrical insulation, and thermal management. Any components that could pose even a minor hazard should be properly enclosed or isolated from the user. By prioritizing these safety measures, we aim to ensure that our digital synthesizer remains safe and accessible to all users.