Shayaan’s Update 02/07

This week we started flushing out our design more. We presented our proposal in class and now are finding parts that fit our specific needs. I am currently doing some research to find what FPGA is best for our application. The ECE capstone inventory has DE0-nano, Ultra 96-V2, Radiano CS-ULX3S-01, and DE10-Standard. I am still figuring out what specs are required for our use case, but we would like to have 1 USB port, one port to connect to external DAC, enough processing components to handle 4 voices, and enough memory to handle delay effect bottleneck. Preliminary calculations suggest we will need 50-100 DSP slices, 200 Mhz clock, and 500kb internal memory.