This week, the team continued working on the core modules in Verilog, while also getting the FPGA ready for testing our implementation on hardware. We’ve got a MIDI controller in the mail as well, which will be all we need to test that the signal propagates through the pipeline correctly.
Daniel began writing wrappers for the Quartus side of our design, starting on getting the modules we already have to synthesize. Shayaan began writing MATLAB tests, which will allow for a much faster checking of our work, by virtue of being able to play directly samples generated from MATLAB, without having to go to hardware. This way, we can ensure what we intend to design will sound the way we expect it to. Jake continued working on the ADSR envelope generator, fixing issues as they arose in a test-bench.