This week, Shayaan finished writing and verifying all of our SystemVerilog modules. Much of the design has also been synthesized, leaving only the final pipeline synthesis remaining. Our completed signal chain will follow the structure: Oscillators -> Filters -> Envelope -> Effects. Once the full pipeline is synthesized, we will evaluate how many voices our FPGA can support given resource constraints.
We are also planning to enhance the system by adding an envelope to modulate the filter cutoff frequency, which should produce a more dynamic sound. In addition, our MIDI keyboard recently arrived, and Jake and Daniel have begun working on transmitting MIDI commands to the FPGA. We are currently encountering some difficulties sending commands directly, so we may need to use a computer as an intermediary.
Daniel is also working on developing a GUI on a computer that will provide detailed control over the synthesizer and offer a more intuitive visualization of our pipeline. The interface will feature a drag-and-drop block diagram, allowing users to easily add and configure effects, filters, and envelopes within the signal chain.
This week, we also performed final verification of our synthesizer. We measured the frequency of the waveforms generated by the FPGA and compared them to the desired target frequencies. We also computed FFTs of our oscillator outputs to evaluate how closely the generated waveforms match their ideal forms. For example, we analyzed the FFT of a square wave to confirm the presence of only odd harmonics. While it is easy to hear whether a filter behaves as a high-pass or low-pass filter, we additionally used FFT analysis to quantitatively examine how the filter affects different frequency components.
Finally, we organized a session where friends will use our FPGA synthesizer to provide validation data. We plan to discuss both the results and the evaluation methods in our presentation.