This week, I made significant progress in writing and synthesizing our effects set. At this point, all of our SystemVerilog modules have been written and verified against our MATLAB pipeline using bit-by-bit verification. This process involves generating an expected hex file from the MATLAB pipeline and ensuring that the SystemVerilog output matches it exactly.
I have written and tested the Delay, Echo, Reverb, Redux, and Distortion modules, and I have successfully synthesized Delay, Echo, Redux, and Distortion. I plan to synthesize Reverb shortly. There is still a small bug in our Envelope module that I am actively working to resolve.
The next step is to integrate all of these components into a final top-level module and evaluate how many voices we can support given the FPGA resource constraints. Another major aspect of our project, which we discussed earlier in the year, is developing a program that takes an input sound and determines how to recreate it using our FPGA synthesizer. This includes identifying the appropriate frequencies, filters, envelopes, and effects needed to approximate the original sound. Once the top module is complete, I will focus on building this program and aim to bring it to a presentable state before demo day.
One of the most important lessons I learned during this project is the value of thorough verification. There are many approaches to verification, but using bit-by-bit comparison with a golden model proved especially effective. When issues arose during synthesis, this method allowed us to quickly isolate and identify the source of the problem because we had high confidence in the correctness of verified components.
I also gained experience working with proprietary IP, which can be quite cumbersome. Since we are using an Intel FPGA, we rely on Quartus IP blocks to drive the DAC for audio output. Integrating and understanding these components took significantly longer than expected due to the complexity and limited transparency of the documentation. Additionally, my team is working on interfacing with a MIDI keyboard, which may require further interaction with proprietary IP. Navigating documentation and implementing even basic functionality often required substantial time and effort.