This week, I focused on the initial design of the oscillator, including defining the overall architecture, estimating the device sizing, and setting the key performance targets. The current design is aimed at achieving an oscillation frequency in the 50–100 MHz range under a 5 V supply, while keeping the total power consumption below 10 mW and the active core area within approximately 1 mm². I also worked on selecting preliminary transistor dimensions and passive component values to balance frequency stability, output swing, and layout efficiency. Overall, the design specifications and size budget have been established, and the next step will be schematic refinement and simulation-based verification of the oscillator performance.
Team Status Report for 3/14
Progress:
This week, our team continued transitioning from early device characterization into the oscillator integration and implementation phase of the project. Building on the first-pass fabrication and measurement results from the prior week, we spent time refining how those results should inform the oscillator design direction, expected operating behavior, and the supporting test infrastructure. In particular, the measured NMOS, resistor, and MOSCAP data from the first iteration helped give us a more realistic understanding of the practical device constraints that the oscillator design must satisfy.
At the same time, progress was made on the supporting hardware side through continued drafting of the test bench PCB and preparation for eventual oscillator bring-up. This helps position the team to move more quickly once the final oscillator design is locked. Overall, this week was less about generating major new measurement results and more about using what we learned from first-iteration characterization to support the next design step.
Schedule/Updates:
At the team level, we are currently about one to two weeks behind schedule due to delays in finalizing the oscillator design and implementation. While characterization results from the first iteration have provided useful guidance and helped narrow the design space, the project is still waiting on the oscillator design to be completed before several downstream tasks can fully proceed. In particular, finalization of the test bench PCB, oscillator integration planning, and follow-on demo infrastructure all depend on having the oscillator design available and understanding its expected operating range and behavior.
At this point, the main path to recovering schedule is to finalize the oscillator design as soon as possible and then move quickly on integration, PCB completion, and fabrication-related next steps. In the meantime, the team has been using the available time to prepare supporting infrastructure and reduce as much downstream delay as possible once the oscillator is ready.
Upcoming Deliverables:
Next week, the team’s highest priority is to finalize a viable oscillator design and begin translating that design into concrete implementation and testing steps. This includes incorporating the finalized oscillator into the test bench PCB, completing the PCB design so it can be ordered on time, and preparing for the next phase of bring-up and characterization.
In parallel, the team also needs to continue preparing for the interim design milestone, which is now only a few weeks away. If early oscillator performance data becomes available soon enough, we also want to begin using those results to inform demo PCB planning and broader system integration decisions. Overall, the main deliverable for next week is to lock the oscillator direction and convert the current characterization-informed planning into concrete hardware progress, such as in finalizing and ordering the test PCB.
Jim’s Status Report for 3/14
Accomplished:
This week, I continued working on the test and measurement infrastructure side of the project by drafting the test bench PCB and preparing for eventual integration with the oscillator design. Even though the final oscillator schematic is still being finalized, this work was still useful because it let me make progress on the supporting hardware and think through the practical constraints that the final design will need to satisfy. In particular, drafting the PCB helped me better understand how the oscillator interface, probing structure, and bring-up flow should be organized once the design is available.
In addition, I also worked on the ethics assignment this week. Although this was separate from the hardware implementation itself, it was still useful in thinking about how our design and characterization workflow may be used by future students and lab users, and how we should communicate the intended use and limitations of the system.
Progress/Schedule:
I am currently on schedule for my portion of the project. I have already started drafting the test bench PCB, which puts me in a good position to move quickly once the final oscillator design is available from Charlie, which is expected by tomorrow or Monday (3/15–3/16). At this stage, the main remaining work on my end is to incorporate the finalized oscillator design into the PCB and then push the design toward completion.
In the meantime, I have been using the available time to prepare as much of the test infrastructure as possible in advance so that I can accelerate once the oscillator implementation is finalized. I have also started thinking ahead about the demo PCB, although that work still depends on the final oscillator design and its measured operating behavior.
Upcoming Deliverables:
Next week, my main priority is to incorporate the finalized oscillator design into the test bench PCB and complete that design. My goal is to finalize the test PCB by the end of next week so that it can be ordered on time. In parallel, I also want to continue preparing for the interim design milestone, which is coming up in about three weeks.
If oscillator performance measurements become available soon enough, I will also begin translating those results into early demo PCB planning so that I can start drafting that design as soon as possible. Overall, my focus for next week is to finish the test PCB and prepare the next stage of measurement and integration work.
Ethan’s Status Report for 3/7
Accomplished:
This week, I have finished our own design of the NMOS process, and it’s waiting to be tested. I have also drafted a process flow for implementing all three components into a single chip and am currently working with Jay to see its viability or any further simplification. I have also got trained on HF, so all the process can be done by myself (still needs the buddy system) so that I’m not limited to Jay’s availability to do etching.
Progress/Schedule
We are still on schedule, once I have got the first chip that has all three basic components on, it should be a very simple process of repeating the same thing over and over again until we get something that is high performance.
Upcoming Deliverables
By next week, I should receive the design from Charlie and begin processing the first version of our actual device, in the meantime, I’ll fabricate a test sample that is just the basic component on their own.
Team Status Report for 3/7
Progress:
This week, our team completed and submitted the final Design Review (DR) report while continuing to build out the characterization-driven foundation of the project. A major step forward was that we were able to move beyond only completing fabrication of the template NMOS devices and instead begin organizing, analyzing, and interpreting real first-iteration measurement data, including NMOS I–V behavior, resistor/TLM measurements, and MOSCAP C–V trends. This gave the team a much stronger quantitative understanding of current device behavior and helped convert several earlier design assumptions into more concrete, measured expectations. Overall, this week marked an important transition from initial fabrication success into a more grounded characterization-to-design feedback loop.
Schedule/Updates:
Overall, the project remains on schedule. With the Design Review report completed and first-pass characterization data now available, we are in a much better position to refine our device and oscillator assumptions using measured silicon behavior rather than relying primarily on estimates. Compared to last week, the team now has stronger footing in understanding threshold variation, drive current, leakage behavior, resistor scaling, and MOSCAP trends, all of which are important for the next design phase. This means we can now progress more confidently, in line with our planned schedule, toward finalizing a potential oscillator design and fabrication steps.
Upcoming Deliverables
Next week, the team’s priorities are to continue supporting characterization where needed based on the current fabrication results, translate the measured device behavior into concrete oscillator design constraints, and finalize an updated project schedule for moving forward. Most importantly, by the end of this week, we need to guarantee that we finalize a viable oscillator design and begin its initial fabrication steps so that the project continues progressing on a realistic implementation timeline. In addition, we will need to flesh out a more concrete fabrication and iteration timeline as we begin executing on our first oscillator design, as we did during our template NMOS run in February.
Jim’s Status Report for 3/7
Accomplished:
This week, I helped complete and submit our final Design Review (DR) report while also continuing work on the characterization and test infrastructure side of the project. A major milestone this week was that we were able to move beyond only having fabricated template NMOS devices and instead begin organizing and analyzing real measurement results from the first iteration, including NMOS I–V behavior, resistor/TLM measurements, and MOSCAP C–V trends. Through analyzing and exploring the data for the DR , I was able to develop better expectations and intuition on how future iteration data exploration and analysis will look like.
In addition, on my end, this was especially useful because it gave me a much clearer picture of the practical electrical constraints that the final oscillator bring-up flow and PCB interface will need to support.
Progress/Schedule:
We are on schedule overall and have successfully transitioned from the initial fabrication milestone into the first real characterization-to-design loop. Compared to last week, we now have stronger quantitative footing for the project since the measured first-pass device data has started to establish baseline expectations for threshold variation, drive current, leakage, resistor behavior, and MOSCAP behavior. This puts us in a better position to refine oscillator assumptions and make the next iteration more grounded in measured silicon rather than prior estimates alone. We can now progress, as indicated by schedule, on finalizing a potential oscillator design.
Upcoming Deliverables:
Next week, my priorities are to continue supporting device characterization where needed given fabrication-resulting data, help narrow the practical oscillator bring-up requirements based on the measured data, and resume more direct progress on the PCB/test interface with these updated constraints in mind. By the end of next week, we should be in a position to more confidently lock the initial oscillator implementation direction and translate the current characterization results into concrete testbench and integration decisions for the next phase of the project.
Charlie’s Status Report for 2/21
Accomplished
This week I supported the Design Review presentation and refined our oscillator design direction. I also compiled a concrete list of device parameters to measure from the completed V1 template NMOS to establish baseline constraints for the next iteration.
Progress/Schedule
We are on schedule overall, with V1 template NMOS fabrication completed and the RIE etch process now stable. Our critical path is now shifting from fabrication to measurement/characterization so we can lock baseline device assumptions for the next iteration.
Deliverables
Next week I will join Jim and Hackerfab to bring up and characterize the V1 NMOS devices and extract quantitative baseline metrics needed for both the V2 template iteration and oscillator sizing. Using those results, I will update the oscillator schematic/design assumptions and help translate measured constraints into concrete next-step design choices for Ethan’s upcoming fabrication planning.
Ethan’s Status Report for 2/21
Accomplished:
This week, I’ve further refined the RIE process, now it works pretty flawlessly. Thanks to some members of the Hackerfab, we now have many devices ready to be measured, some initial measurement has been done, more to come next week. I have since catched up with the process and should have my own first iteration this weekend.
Progress/Schedule
We have begun discussing the process for fabricating NMOS, resistor, and MOSCap on the same chip. The main challenge here is the diffusion step as right now, each of them requires different time in the furnace, plus NMOS process is much longer and has two diffusion processes compared to resistor or MOSCap so we are currently working on a process that can address this issue.
Upcoming Deliverables
Outline for the final process that we will use to fabricate our actual device, as we shift from initial testing to initial fabrication of our first iteration of devices. Once the measurements are in, we will have more information as to what our limitations are.
Team Status Report for 2/21
Progress:
This week we completed our Design Review presentation and successfully finished the first iteration of template NMOS fabrication. Importantly, HackerFab has now resolved the ICP-RIE etching issue, so the process is working reliably again and unblocking continued device fabrication. With V1 devices in hand, the project now transitions from fabrication execution into bring-up and quantitative characterization, which will establish the baseline device parameters and expectations needed to refine the oscillator design, inform the next NMOS fabrication, and steadily progress towards oscillator fabrication.
Schedule/Updates:
Overall, we are on schedule relative to our February/pre–spring break plan. The V1 fabrication milestone was met as planned with underlying fabrication issues fully resolved. Due to scheduling constraints, full characterization under Hackerfab guidance could not be completed immediately and earlier, but the team expects to complete bring-up and collect quantitative device metrics by the end of next week to remain compliant to the project timeline.
Upcoming Deliverables
Next week’s priority is to close the loop on Iteration 1 by performing device testing/characterization (led by Charlie and Jim, with HackerFab support) and generating concrete quantitative parameters (IV curves, safe operating voltage window, leakage behavior) that can be fed back into: the V2 template NMOS iteration planning now that the etch process is restored, as well as the Oscillator design refinement, grounded in measured device behavior rather than previous assumptions.
In parallel, the team will produce the Design Review Report for submission by 2/27, incorporating design review feedback and documenting the fabrication workflow, current results, and updated validation plan.
Evidence and Photos of Current Status
The hyperlink leads to the proposal presentation that we presented this week. Slides 6-8 shows photos of the fabrication process taken in Hackerfab. For next week, we will upload pictures and process of measurements and characterization.
Jim’s Status Report for 2/21
Accomplished:
This week, we completed our design review presentation as well as the first iteration of fabrication of our template NMOS. I had a main stake in creating the presentation along with Ethan, and in parallel continued my personal progress of developing the test and demo PCB for the final oscillator. On my end, I have refined my PCB draft for bring-up and characterization of the oscillator. However, this will be temporarily put on hold as the main focus has shifted to testing and characterizing the newly fabbed NMOS Templates so that Ethan have feedback for v2 iteration on the template NMOS, and that we can start beginning to develop a baseline specs on the oscillator design and performance yields.
Progress/Schedule
We are just on schedule with our initial February/pre-spring break schedule with our first iteration NMOS fabbed done Feb 19th. As such, we are well within our timeline to progress into the characterization phase of this iteration.
Upcoming Deliverables
Given scheduling conflict, we won’t be able to conduct the characterization earlier within this week. However, we will be able to bring-up, test, characterize, and produce quantitative metrics and specs before the end of next week. By the end of the week, to remain on schedule, we must fully wrap up the first iteration on the template NMOS and give Ethan feedback on the NMOS behavior and specs so we can start the second iteration on NMOS as soon as possible. In parallel, we must also work and produce a final presentable design review report by 2/27.