Posted on

Ethan’s Status Report for 2/14

Accomplished

This week, I have continued the fabrication process for our first batch of NMOS. However, challenges were encountered during the ICP RIE process where our chip failed to etch as expected after repeated multiple attempts. During the process, two of our chips were basically destroyed. After some investigation through AFM and a report from the rest of the NMOS group who were successful in doing the RIE, I have since found and resolved the issue.

Progress/Schedule

The previous setback has caused a measurable set back in my schedule. Our initial optimistic goal was to have them done this week, but due to the issue that we encountered, the plan is now to have them sometime this week (Tuesday/Wednesday). On top of that, since Hackerfab is also restoring the process and has a dedicated NMOS team working on it, we have about 6 chips that are planned to be finished by this Wednesday so regardless of my own progress, we should be getting some basic measurements this week.

Upcoming Deliverables

Next week, we should have some devices ready to be measured, and I should be able to fabricate the first batch as I continue to learn and refine the process throughout each try. I will also start the design on the capacitor and resistor components.

Posted on

Team Status Report for 2/14

Progress:

  • Fabrication Iteration: the first template NMOS fabrication run did not yield a working batch, so the team is restarting the fab process for the next iteration.
  • Schedule Status: the restart and updated projected finish time is still within our original timeline/buffer set in the 2/7 team status report. The team expects the fab to complete within this week and subject to bring-up and characterization.
  • Parallel Work Continues: While fab restarts, we are (1) finalizing the oscillator schematic direction and (2) preparing the test/measurement workflow so the final oscillator can be characterized quickly when we bring-up.

Risk Management:

The primary risk for this week is the schedule uncertainty from the fab restart. Given we have already exhausted our buffer time period in the conservative timeline set in the 2/7 team status report, if the next run slips or encounters another failure, it would compress the remaining time for bring-up and characterization as well as our goal of going through and documenting the entire first iteration. We are mitigating this risk by keeping the design, characterization, and testing planning in parallel so no time is wasted once the hardware is fabricated and functional. This could compensate for the time lost if the next few fab runs also experience failures. 

Upcoming Schedule: 

Despite the fab process restart, we are still in a good position to meet the original timeline and remain on track relative to the buffer that we established in the 2/7 team status report. Once the fab is successfully completed, we must move fast to begin the characterization and measurement process in order to meet our original goal of finishing and documenting the first iteration before spring break. In the meantime, the team, in addition to the characterization and design planning work in parallel, has begun working on the design presentation slides for next week.

Week-Specific Design Impact Considerations.

With regards to this week’s specific design impact considerations questions, part A is written by Jim, part B is written by Charlie, and part C is written by Ethan.

Part A: Our fabbed oscillator and documented, repeatable bring-up workflow improve safety by greatly reducing wiring/probing and trial-and-error during lab testing and measuring. This lowers the likelihood of miswiring, improper loading, and accidental device/equipment damage during power-up and characterization. By providing a repeatable testing infrastructure (defined interfaces, checklists, and measurement access points), we reduce ad-hoc setups and make safe bring-up the default. The workflow also standardizes safe sequencing and measurement steps so new teams can follow a known process instead of improvising on the spot. Overall, it creates a safer and more predictable lab environment while improving the reliability of our measurements.

Part B: Our fabbed oscillator and documented workflow strengthen the HackerFab community as an extended student/instructor group by providing shared infrastructure that teams can organize around. By pairing the design with a repeatable bring-up and measurement workflow, future projects can adopt a common baseline instead of each team developing isolated processes. This improves collaboration across teams and mentors because everyone can align on the same interfaces, expectations, and validation steps. Overall, it supports continuity and collaboration within the HackerFab and ECE community by making our process and lessons learned accessible to future students.

Part C: Our fabbed oscillator and documented workflow improve economic efficiency and saves cost in HackerFab by creating an established, reusable baseline that future teams can use instead of repeatedly spending time and exhausting fabrication resources reinventing basic oscillator bring-up. This benefits not only teams building future oscillators, but also teams building more complex systems that depend on an oscillator (mixed-signal components) as they can start from a validated reference. Through our documentation, we reduce recurring setup/debug labor and increase the likelihood that fabrication runs and lab time yield actionable results. Overall, this also increases the return and availability of shared HackerFab resources (fab slots, equipment time, and staff/TA support) by making downstream projects faster and cheaper to execute.

Posted on

Jim’s Status Report for 2/14

Accomplished

This week, progress on the physical device was mainly on the fabrication side. Ethan completed an initial template NMOS iteration but the batch did not work out, so the team is restarting the fab run. In parallel, since we are far from creating the final oscillator to test/measure yet, I continued my own schedule in advancing the first draft of the test/measurement infrastructure PCB design for the full oscillator. This is specifically targeted towards bring-up and characterization when the final oscillator is fabricated. Note that for measuring and characterizing the NMOS template, the Hackerfab internal tools suffice by themselves. 

Progress/Schedule

We are still on schedule overall. Despite having to restart, the fab timeline is still feasible referring to the Feb. 19 latest completion date set during the 2/7 team status report. Ethan is projecting to finish another batch before that, so this fabrication reset is possible. For my schedule, my PCB work is proceeding in parallel as I have already completed a rough first draft of the design. There is no pressure/rush on my end for now given the emphasis on fabricating and in-house characterizing the NMOS, but I do need to update and keep the PCB design flexible/modular so we can quickly incorporate any new constraints and updates from the fabrication process.

Upcoming Deliverables

Next week, I will refine the PCB draft into a more complete first-pass plan and align the PCB interfaces for any updates and new constraints reported from the fabrication process. In addition, since the fabrication for the template NMOS is projected to be done soon, I will have to go to Hackerfab and help bring-up and characterize the NMOS and help the team plan for the next iteration.

Posted on

Charlie’s Status Report for 2/7

Accomplish

This week I evaluated several simple oscillator architectures and selected an easy-to-implement schematic direction. I drafted an initial block-level schematic and documented design tradeoffs to prepare for full transistor-level implementation.

Progress/Schedule

Is your progress on schedule or behind?
The project is currently on schedule. The oscillator architecture selection was completed as planned, enabling us to move directly into schematic implementation next week without major delays.

Deliverables

Next week I plan to complete the full oscillator schematic, including tuning and buffering blocks, and set up basic simulations to verify startup behavior and frequency range.

Posted on

Ethan’s Status Report for 2/7

Accomplished

This week, I met with the Hackerfab members again and joined their session on NMOS Process training and general equipment training. I have also started the process of fabricating the first batch of our test MOSFET to get an initial calibration. So far, I’m certified to use the Hackerfab during daytime over weekdays and I’m trained on all the relevant processes except for the BOE wet etching, which uses HF, and Hackerfab has protocols that prevent undergraduate students from using HF. However, Hackerfab director Jay Kunselman agreed to help me whenever I needed to do BOE wet etching.

Progress/Schedule

I’m on schedule in terms of fabrication, the first batch has already been through the process of doping the polysilicon gate, with a few patterning and doping of the source and drain left to be completed. In our schedule, we are currently still in the phase of calibration and testing the process, so the sooner I can get a few working MOSFETs up, the sooner we can start implementing our design.

Upcoming Deliverables

I expect the first batch of chips (4 of them) to be fully fabbed by the end of next week and wirebond ASAP so Charlie and Jim can start on the measurement, if things go well. Regardless, the latest time for this would be the week after, at which if I still fail to fabricate a MOSFET, then we will need to reconsider our approach. I forgot to take a picture of the chip right now but I’ll do that next week once I patterned the source/drain and have made contact.

Posted on

Team Status Report for 2/7

Team Progress/Schedule

This week, we finalized and delivered our project proposal presentation, aligned on project scope and responsibilities, and confirmed our initial project timeline (Gantt chart). Ethan has already begun fabricating the first template NMOS iteration to enable early bring-up and initial measurements before proceeding into full oscillator iterations.

Our project timeline for the rest of February is as follows. Note that the dates are very conservative and all worst-case/latest projections. We expect to be at or ahead of this schedule if fabrication and bring-up proceed expectedly:

  • By February 19 (Latest): Complete fabrication of first template NMOS iteration.
  • By February 23: Finish initial bring-up and generate the first characterization curves and measurements on template NMOS using Hackerfab tools.
  • By February 28: Complete first-iteration characterization and summarize results to guide the next design/iteration steps. 

 

Risk Mitigation

The main risks, as mentioned in the project proposal presentation, are fabrication or bring-up issues that delay initial measurements as well as measurement limitations (probing/loading effects) that delay clean characterization. We are mitigating this by using a template NMOS first and relying on existing HackerFab tools for the initial characterization phase. Given that we already started the process of doing the first fabrication of the template, if issues arise, we will prioritize a minimal set of essential characterization metrics first and defer non-critical work until after we confirm basic device behavior.

Design/Requirements Changes

No major changes were made to the system requirements, block diagram, or specs this week as we just started the first step. We did clarify the execution plan to start with a template NMOS fabrication + characterization phase before locking later iteration details (including the full demo/test PCB). This reduces risk by validating measurement assumptions early, at the cost of keeping some downstream PCB/demo details provisional until first data is collected. We will mitigate this by continuing PCB planning and SPICE validation in parallel so the design can converge quickly once early measurements are available.

Posted on

Jim’s Status Report for 2/7

Accomplished

This week, I focused on preparing our project proposal presentation materials and helping the team communicate and craft a clear initial project timeline. I led and created the majority of the proposal slide deck, namely the slides on use-case, use-case requirements, technical challenges, iterative workflow diagram, and project management plans. On Wednesday, I presented the proposal on behalf of the team to our assigned professor lead and TA. I also began scoping the requirements for the test/demo PCB that I will own (interfaces, measurement needs, and constraints) so the PCB design can proceed in parallel while the first template NMOS iteration is being fabricated and brought up for initial measurements.

Progress/Schedule

I am on schedule for our initial timeline. This week’s focus was on fleshing out the project presentation and finer details to align with the milestones. With the proposal successfully delivered and with my partner beginning the first template NMOS fabrication process, we are on pace with our planned Gantt chart. I am prepared and set-up to begin deeper technical execution next week while fabrication progresses in parallel to my assigned work scope. 

Upcoming Deliverables

 Next week, I will produce a first-pass draft of the test/demo PCB plan and begin SPICE-level simulations to validate key measurement assumptions (main emphasis on fleshing out the finer technical details on loading/buffering and power delivery considerations). Note that although early measurements can leverage existing HackerFab tooling for the first template NMOS characterization, a well-defined PCB test harness will be crucial for repeatable characterization and later iteration bring-up/demonstration on the full oscillator.