Accomplished:
I have received feedback on our V2 chip, there are few issues that need to be addressed. First, the bond pads need to be increased due to the difficulties last time. Also, there has been a design flaw from Charlie’s end where an additional resistor is needed between gate and ground, I have since completely reworked all of my etch masks to address this change in design. V3 is currently under fabrication.
Progress/Schedule:
I have managed to begin and complete the first few processes of the fabrication as of Saturday night. However there has been an issue with RIE etching as Hackerfab ran out of SF6. I am currently communicating with Jay to see if the delivery can be made before Monday, otherwise, I will have to use the 790 RIE from the nanofab as an alternative. I’m suspecting some parameter changes due to different machinery, but due to the selectiveness of SF6 on polysilicon and silicon oxide, the task should still be manageable. That does delay my timeline by a day or two, which may cause issues.
Upcoming Deliverables:
My plan is to deliver V3 by Monday for Jim and Charlie to test and finalize their part. The previous v2 has shown great properties that are nearly 100% consistent with expectation, therefore, I believe that if our calculation is done right without design oversight, this could very much work right off the bat. There will be 4 functional devices on the next chip, which I will cleave into individual chip before wirebond, which will then directly integrate into the PCB.


