Ethan’s Status Report for 4/25

Accomplished:
I have received feedback on our V2 chip, there are few issues that need to be addressed. First, the bond pads need to be increased due to the difficulties last time. Also, there has been a design flaw from Charlie’s end where an additional resistor is needed between gate and ground, I have since completely reworked all of my etch masks to address this change in design. V3 is currently under fabrication.

Progress/Schedule:
I have managed to begin and complete the first few processes of the fabrication as of Saturday night. However there has been an issue with RIE etching as Hackerfab ran out of SF6. I am currently communicating with Jay to see if the delivery can be made before Monday, otherwise, I will have to use the 790 RIE from the nanofab as an alternative. I’m suspecting some parameter changes due to different machinery, but due to the selectiveness of SF6 on polysilicon and silicon oxide, the task should still be manageable. That does delay my timeline by a day or two, which may cause issues.

Upcoming Deliverables:
My plan is to deliver V3 by Monday for Jim and Charlie to test and finalize their part. The previous v2 has shown great properties that are nearly 100% consistent with expectation, therefore, I believe that if our calculation is done right without design oversight, this could very much work right off the bat. There will be 4 functional devices on the next chip, which I will cleave into individual chip before wirebond, which will then directly integrate into the PCB.

Ethan’s Status Report for 4/18

Accomplished:
Finished fabricating V2 of our chip, yield rate is much better and the measured results are consistent. Then pass it on to Charlie and Jim on measurement and help them set up the probe station.

Progress/Schedule:
Currently working on wirebonding the last chip since probing 6 pads at the same time prove to be difficult, and we have recognized a potential issue with the design, and are actively working on a V3 design.

Upcoming Deliverables:
By next week, we should have V3 done if fabrication goes well, the recent spill of Type A Al Etchant disabled the wet etch bench in the Hackerfab. Jay told us that it can be fixed by the end of the week, so I plan on finishing V3 during the weekend.

Ethan’s Status Report for 4/4

Accomplished:
I let Jim and Charlie measure the chip that I fabbed last week and provide direction on specific parameters that I need to continue my fabrication process. They took those measurements and have provided me with direction for improvement for our next iteration. I have since modified the design and begun the fabrication process of the next iteration.

Progress/Schedule:
We are still recovering from the two weeks of lost in time as I’m not certain how many iteration it would take for us to get the chip starts to oscillate, there are many unknown variables from the fabrication stand point that really asks for multiple iterations, but I’m on track to deliver two more iterations based on the time remaining.

Upcoming Deliverables:
I’ll finish up the devices by wednesday before the spring carnival before I take a break and leave Pittsburgh, in the meantime, Charlie and Jim can work on measuring the devices so I can get ready to modify things for the next iteration immediately after I come back.

Ethan’s Status Report for 3/28

Accomplished:
Worked with Charlie to finalize the schematic, then created the layout and the masks for lithography. Then spent 15 hours and went through all fabrication steps to create our first batches of actual devices. The yield rate is around 20%, with two chips of different doping levels on the resistor. 

Progress/Schedule:
We are a little bit off schedule, we expect to have a working first iteration ready to present on Monday, but as it stands, we might have to delay it to Wednesday. Most of my work has concluded, and what is left is just the iterative process of refining our parameters and figuring out what is best.

Upcoming Deliverables:
Measurement should be conducted over next week and we will continue to fabricate more batches until we can finalize on our final deliverable.

Ethan’s Status Report for 3/21

Accomplished:
This week, I stayed involved in ongoing design discussions and worked with Charlie on implementation considerations as the oscillator design continued to take shape. My main focus was making sure I am aligned with the design direction and ready to transition into fabrication once the remaining design details are resolved.

Progress/Schedule:
I am currently on schedule for my portion of the project. At this point, my next major task depends on completion of the oscillator design, but aside from that dependency, I am in a good position to move forward quickly.

Upcoming Deliverables:
For next week, I plan to begin fabrication work as soon as the design is fully ready. In the meantime, I will continue staying engaged in team discussions so that I am prepared to support a smooth transition into the next phase.

Ethan’s Status Report for 3/14

Accomplished:

Formed a complete process flow on fabublox and optimized it with the help of Jay. Begun the validation of the process, with a few more steps left to have a completed chip.

Progress/Schedule

Most of my development work ends here, all there is left is for me to use the process that I have validated to create our actual device based on Charlie’s design.

Upcoming Deliverables

Finish the last few steps of the validation process and have the rest of the team measure it for more data, especially on high frequency behavior. And hopefully begin fabrication of the actual device as soon as possible.

Ethan’s Status Report for 3/7

Accomplished:

This week, I have finished our own design of the NMOS process, and it’s waiting to be tested. I have also drafted a process flow for implementing all three components into a single chip and am currently working with Jay to see its viability or any further simplification. I have also got trained on HF, so all the process can be done by myself (still needs the buddy system) so that I’m not limited to Jay’s availability to do etching.

Progress/Schedule

We are still on schedule, once I have got the first chip that has all three basic components on, it should be a very simple process of repeating the same thing over and over again until we get something that is high performance.

Upcoming Deliverables

By next week, I should receive the design from Charlie and begin processing the first version of our actual device, in the meantime, I’ll fabricate a test sample that is just the basic component on their own.

Ethan’s Status Report for 2/21

Accomplished:

This week, I’ve further refined the RIE process, now it works pretty flawlessly. Thanks to some members of the Hackerfab, we now have many devices ready to be measured, some initial measurement has been done, more to come next week. I have since catched up with the process and should have my own first iteration this weekend.

Very clean etch step, image taken under optical microscope in dark field.

Progress/Schedule

We have begun discussing the process for fabricating NMOS, resistor, and MOSCap on the same chip. The main challenge here is the diffusion step as right now, each of them requires different time in the furnace, plus NMOS process is much longer and has two diffusion processes compared to resistor or MOSCap so we are currently working on a process that can address this issue.

Upcoming Deliverables

Outline for the final process that we will use to fabricate our actual device, as we shift from initial testing to initial fabrication of our first iteration of devices. Once the measurements are in, we will have more information as to what our limitations are.

Ethan’s Status Report for 2/14

Accomplished

This week, I have continued the fabrication process for our first batch of NMOS. However, challenges were encountered during the ICP RIE process where our chip failed to etch as expected after repeated multiple attempts. During the process, two of our chips were basically destroyed. After some investigation through AFM and a report from the rest of the NMOS group who were successful in doing the RIE, I have since found and resolved the issue.

Progress/Schedule

The previous setback has caused a measurable set back in my schedule. Our initial optimistic goal was to have them done this week, but due to the issue that we encountered, the plan is now to have them sometime this week (Tuesday/Wednesday). On top of that, since Hackerfab is also restoring the process and has a dedicated NMOS team working on it, we have about 6 chips that are planned to be finished by this Wednesday so regardless of my own progress, we should be getting some basic measurements this week.

Upcoming Deliverables

Next week, we should have some devices ready to be measured, and I should be able to fabricate the first batch as I continue to learn and refine the process throughout each try. I will also start the design on the capacitor and resistor components.

Ethan’s Status Report for 2/7

Accomplished

This week, I met with the Hackerfab members again and joined their session on NMOS Process training and general equipment training. I have also started the process of fabricating the first batch of our test MOSFET to get an initial calibration. So far, I’m certified to use the Hackerfab during daytime over weekdays and I’m trained on all the relevant processes except for the BOE wet etching, which uses HF, and Hackerfab has protocols that prevent undergraduate students from using HF. However, Hackerfab director Jay Kunselman agreed to help me whenever I needed to do BOE wet etching.

Progress/Schedule

I’m on schedule in terms of fabrication, the first batch has already been through the process of doping the polysilicon gate, with a few patterning and doping of the source and drain left to be completed. In our schedule, we are currently still in the phase of calibration and testing the process, so the sooner I can get a few working MOSFETs up, the sooner we can start implementing our design.

Upcoming Deliverables

I expect the first batch of chips (4 of them) to be fully fabbed by the end of next week and wirebond ASAP so Charlie and Jim can start on the measurement, if things go well. Regardless, the latest time for this would be the week after, at which if I still fail to fabricate a MOSFET, then we will need to reconsider our approach. I forgot to take a picture of the chip right now but I’ll do that next week once I patterned the source/drain and have made contact.