Progress:
This week, the team focused on final-stage oscillator testing for V2, V3 fabrication, PCB assembly, and final demo preparation. During testing, the circuit was able to turn on the LEDs, which was an encouraging sign that the chip and external setup were producing meaningful output behavior. However, confirming actual oscillation remained difficult because the setup required six delicate probe connections routed into a breadboard. Even very small wire or probe movement could disrupt the contacts, which made it hard to reliably connect the oscilloscope or additional inspection circuitry. The team also observed some unexpected test point voltages, but because of the instability of the probing setup, it was difficult to determine whether those came from the device, the circuit, or the measurement setup. Jim worked on PCB soldering and integration preparation, with the main remaining dependency being final confirmation of the off-chip capacitor values. Ethan focused on V3 fabrication and the updated wirebonding path after the V2 aluminum adhesion issue. Charlie supported the circuit side by providing schematic revisions, design ideas, and value calculations to guide the final testing and V3 approach.

Schedule/Updates:
The team is still progressing toward the final demo, but the schedule is tight because V3 fabrication, wire-bonding, characterization, and integration all need to happen quickly. Compared to last week, the main update is that V2 showed promising LED behavior, but we still cannot confidently claim stable oscillation without reliable oscilloscope confirmation. The current limitation is not only circuit behavior, but also the practical difficulty of testing a six-pad device through manual probing and breadboard wiring. Because of that, V3 is now the main path for improving final validation. Once V3 is fabricated and wirebonded, testing should become much easier because the team can avoid delicate manual probing and instead use the chip holder and breadboard adapter for more stable circuit connections. This should make oscilloscope testing, voltage inspection, and overall demo integration much more practical.

Upcoming Deliverables:
For next week, the team’s main priorities are to complete V3 fabrication and wire-bonding, test the device using the chip holder and breadboard adapter, finish PCB integration, and prepare all final demo materials. Ethan will focus on completing V3 fabrication and supporting wire-bonding so the chip can be tested in a more reliable integrated setup. Jim will finish the remaining PCB soldering and integration work once the off-chip capacitor values are confirmed, while also supporting V3 characterization and final demo setup. Charlie will continue supporting schematic refinement, circuit value calculations, and testing strategy based on the results from V2 and V3. In parallel, the full team will work on the final handout/writeup, poster board, and video.

Progress:
Over the past two weeks, the team made strong progress across characterization, fabrication, and hardware integration. Jim completed the demo PCB layout, finalized the BOM and remaining component selections, submitted the board for ordering, and received both the fabricated PCB and the remaining supporting materials needed for assembly. In parallel, he completed V2 transistor sweeps and resistance measurements at the probe station, then organized and summarized those results for design validation and final presentation use.

Ethan fabricated V2 for testing and measurement and, because the results looked promising, redeposited aluminum afterward so the devices could be tested more directly. He also began preparing for V3 so the next iteration can be finalized quickly if only minor resistance adjustments are needed. Charlie contributed by building the breadboard-level circuitry for oscillation testing and working through the analog testing setup, including determining the pin access and holder/interface requirements needed to connect the chip into the breadboard environment. Overall, the team has made substantial progress in moving from validation into final-stage testing readiness.

Schedule/Updates:
The team remains on schedule and is now entering the final stretch of the project. Compared to the previous update, the project is in a much stronger position because the demo PCB and materials are now physically in hand, V2 characterization has been completed with encouraging results, and the oscillation testing setup is much closer to ready. The latest measured values are much more aligned with the originally targeted design range than V1, which gives the team better confidence going into final presentation week and demo week. Oscillation testing is beginning tonight, so the next update should reflect whether the current iteration is already achieving the expected behavior or whether further V3 adjustments will be needed.

Upcoming Deliverables:
For next week, the team’s main priorities are to carry out final oscillation testing on the current iteration, confirm whether the measured values and integration setup produce the expected oscillator behavior, and prepare the final presentation materials. Jim will help organize the measured and benchmarked data for the presentation, prepare the demo PCB for final integration, and support continued testing and validation. Ethan will continue refining the chip iteration path and finalize V3 if small design adjustments are needed based on the oscillation results. Charlie will continue supporting the oscillation test setup and final presentation integration. Overall, the team’s next deliverables are to verify oscillator performance, prepare the final presentation, and move the hardware and chip integration into a demo-ready state.

Progress:
This week, the team made strong progress on both characterization and hardware integration. A major focus was collecting empirical measurement data from the fabricated chip to support the next design iteration. Jim spent significant time at the probe station performing transistor sweeps, CVU measurements related to switching behavior, and resistance measurements across on-chip structures. These results gave Ethan the data needed to move forward with the V2 design iteration. In parallel, the team also finalized the demo PCB schematic, moving that work from schematic definition into layout and packaging.

Schedule/Updates:

The team remains on schedule, although the timeline is tight. Compared to last week, the project is now in a much better position because both characterization and PCB schematic work advanced significantly. The main immediate deadline is finishing the demo PCB layout and submitting the order by next Tuesday, along with ordering the remaining supporting materials for the demo setup.

Upcoming Deliverables:
Next week, the team’s main priorities are to complete the V2 design iteration using this week’s measurement results, finalize the demo PCB layout, and place all remaining orders by Tuesday. Ethan will use the characterization data to refine the next chip iteration, while Jim will focus on PCB layout and ordering the remaining components needed for the demo platform. Charlie will continue supporting integration of the finalized oscillator design into the demo setup. Overall, the team is in a good position to turn this week’s measured results into the next round of refinement and implementation.

Progress:
This week, the team made a major step forward by finalizing the initial oscillator design. Charlie completed and locked the first implementation, which allowed the project to move out of the design-finalization stage and into fabrication, integration, and characterization. In parallel, the supporting NMOS analysis was completed to better organize the distributions of gm​, Id, and Vth​ across device types, patterns, and chips, giving the team stronger backing for the final device and parameter dimension choices. On the fabrication side, Ethan completed fab on Friday, and over the weekend Jim is immediately coordinating with HackerFab personnel to arrange time for initial measurements and to make sure the team is prepared for any measurement-specific details before characterization and iteration begins next week.

Schedule/Updates:
Compared to last week, the team is now in a much stronger position. The biggest bottleneck had been completing the oscillator design, but that has now been resolved, and fabrication has also moved forward, allowing the project to transition from design uncertainty into empirical validation. This means the team’s immediate work is now centered on collecting first measurements, preparing for the interim demo, and using the initial results to guide quick follow-up refinements.

Upcoming Deliverables:
Next week, the team’s main priorities are to complete the first round of characterization, continue preparing and presenting for the interim demo, and use the measured results to guide the next iterations. Ethan plans to use the characterization data to support a v2 design iteration, while Jim will work with Charlie to finalize the demo PCB based on a better empirical understanding of the oscillator’s actual performance. With the initial design complete and fabrication underway, the team is now positioned to move quickly on translating the finished design into measured results.

Progress:
This week, the team made meaningful progress toward locking the oscillator implementation. We now have a concrete schematic to build around, and the key device characterization data needed to support final design decisions has been compiled and reviewed. In particular, the NMOS measurement results were revisited in detail to compare Id​, gm​, and Vth​ across chips and patterns, which helped narrow the device choices and provide Charlie with the information needed to finalize values in the design and pending for fab.

On the hardware side, the testbench PCB design is effectively ready pending final pin assignment from the oscillator schematic. In addition, orders have already been placed for the PLCC28 chip holder and the backup PLCC28 through-hole to DIP-28 adapter to support initial bring-up. As a result, much of the supporting infrastructure for early testing is now in place, and the remaining dependency is primarily the finalization of the oscillator design itself.

Schedule/Updates:
Last week, the team was roughly two weeks behind schedule due to delays in locking the oscillator design. Since then, we have reduced that gap and are now closer to less than one week behind, assuming the design is finalized on Monday as planned. The key improvement is that the project has moved from a characterization and planning stage into a concrete implementation stage, with both the schematic direction and the supporting measurement data now largely in place.

At this point, the main remaining bottleneck is final design finalization and the transition into fabrication. Once the schematic and pin assignments are locked, the team is in a good position to move quickly on the remaining integration and bring-up steps. To continue reducing the schedule delay, the team’s focus is to finalize the design promptly and then execute quickly on the now-unblocked downstream tasks, since much of the supporting data and bring-up planning/infrastructure has already been completed in advance.

Upcoming Deliverables:
Next week, the team’s top priority is to finalize the oscillator design quickly and move into fabrication. Once the design is locked, the immediate next steps are fabrication and continue organizing the initial bring-up flow. Since the chip holder and backup adapter have already been ordered, the initial bring-up path is largely prepared; the team is now mainly waiting on final design completion and fabrication to proceed.

Progress:

This week, our team continued transitioning from early device characterization into the oscillator integration and implementation phase of the project. Building on the first-pass fabrication and measurement results from the prior week, we spent time refining how those results should inform the oscillator design direction, expected operating behavior, and the supporting test infrastructure. In particular, the measured NMOS, resistor, and MOSCAP data from the first iteration helped give us a more realistic understanding of the practical device constraints that the oscillator design must satisfy.

At the same time, progress was made on the supporting hardware side through continued drafting of the test bench PCB and preparation for eventual oscillator bring-up. This helps position the team to move more quickly once the final oscillator design is locked. Overall, this week was less about generating major new measurement results and more about using what we learned from first-iteration characterization to support the next design step.

Schedule/Updates:

At the team level, we are currently about one to two weeks behind schedule due to delays in finalizing the oscillator design and implementation. While characterization results from the first iteration have provided useful guidance and helped narrow the design space, the project is still waiting on the oscillator design to be completed before several downstream tasks can fully proceed. In particular, finalization of the test bench PCB, oscillator integration planning, and follow-on demo infrastructure all depend on having the oscillator design available and understanding its expected operating range and behavior.

At this point, the main path to recovering schedule is to finalize the oscillator design as soon as possible and then move quickly on integration, PCB completion, and fabrication-related next steps. In the meantime, the team has been using the available time to prepare supporting infrastructure and reduce as much downstream delay as possible once the oscillator is ready.

Upcoming Deliverables:

Next week, the team’s highest priority is to finalize a viable oscillator design and begin translating that design into concrete implementation and testing steps. This includes incorporating the finalized oscillator into the test bench PCB, completing the PCB design so it can be ordered on time, and preparing for the next phase of bring-up and characterization.

In parallel, the team also needs to continue preparing for the interim design milestone, which is now only a few weeks away. If early oscillator performance data becomes available soon enough, we also want to begin using those results to inform demo PCB planning and broader system integration decisions. Overall, the main deliverable for next week is to lock the oscillator direction and convert the current characterization-informed planning into concrete hardware progress, such as in finalizing and ordering the test PCB.

Progress:

This week, our team completed and submitted the final Design Review (DR) report while continuing to build out the characterization-driven foundation of the project. A major step forward was that we were able to move beyond only completing fabrication of the template NMOS devices and instead begin organizing, analyzing, and interpreting real first-iteration measurement data, including NMOS I–V behavior, resistor/TLM measurements, and MOSCAP C–V trends. This gave the team a much stronger quantitative understanding of current device behavior and helped convert several earlier design assumptions into more concrete, measured expectations. Overall, this week marked an important transition from initial fabrication success into a more grounded characterization-to-design feedback loop.

Schedule/Updates:

Overall, the project remains on schedule. With the Design Review report completed and first-pass characterization data now available, we are in a much better position to refine our device and oscillator assumptions using measured silicon behavior rather than relying primarily on estimates. Compared to last week, the team now has stronger footing in understanding threshold variation, drive current, leakage behavior, resistor scaling, and MOSCAP trends, all of which are important for the next design phase. This means we can now progress more confidently, in line with our planned schedule, toward finalizing a potential oscillator design and fabrication steps.

Upcoming Deliverables

Next week, the team’s priorities are to continue supporting characterization where needed based on the current fabrication results, translate the measured device behavior into concrete oscillator design constraints, and finalize an updated project schedule for moving forward. Most importantly, by the end of this week, we need to guarantee that we finalize a viable oscillator design and begin its initial fabrication steps so that the project continues progressing on a realistic implementation timeline. In addition, we will need to flesh out a more concrete fabrication and iteration timeline as we begin executing on our first oscillator design, as we did during our template NMOS run in February.

Progress: 

This week we completed our Design Review presentation and successfully finished the first iteration of template NMOS fabrication. Importantly, HackerFab has now resolved the ICP-RIE etching issue, so the process is working reliably again and unblocking continued device fabrication. With V1 devices in hand, the project now transitions from fabrication execution into bring-up and quantitative characterization, which will establish the baseline device parameters and expectations needed to refine the oscillator design, inform the next NMOS fabrication, and steadily progress towards oscillator fabrication. 

Schedule/Updates:

Overall, we are on schedule relative to our February/pre–spring break plan. The V1 fabrication milestone was met as planned with underlying fabrication issues fully resolved. Due to scheduling constraints, full characterization under Hackerfab guidance could not be completed immediately and earlier, but the team expects to complete bring-up and collect quantitative device metrics by the end of next week to remain compliant to the project timeline.

Upcoming Deliverables

Next week’s priority is to close the loop on Iteration 1 by performing device testing/characterization (led by Charlie and Jim, with HackerFab support) and generating concrete quantitative parameters (IV curves, safe operating voltage window, leakage behavior) that can be fed back into: the V2 template NMOS iteration planning now that the etch process is restored, as well as the Oscillator design refinement, grounded in measured device behavior rather than previous assumptions.

In parallel, the team will produce the Design Review Report for submission by 2/27, incorporating design review feedback and documenting the fabrication workflow, current results, and updated validation plan.

Evidence and Photos of Current Status

The hyperlink leads to the proposal presentation that we presented this week. Slides 6-8 shows photos of the fabrication process taken in Hackerfab. For next week, we will upload pictures and process of measurements and characterization.

 

Progress:

• Fabrication Iteration: the first template NMOS fabrication run did not yield a working batch, so the team is restarting the fab process for the next iteration.
• Schedule Status: the restart and updated projected finish time is still within our original timeline/buffer set in the 2/7 team status report. The team expects the fab to complete within this week and subject to bring-up and characterization.
• Parallel Work Continues: While fab restarts, we are (1) finalizing the oscillator schematic direction and (2) preparing the test/measurement workflow so the final oscillator can be characterized quickly when we bring-up.

Risk Management:

The primary risk for this week is the schedule uncertainty from the fab restart. Given we have already exhausted our buffer time period in the conservative timeline set in the 2/7 team status report, if the next run slips or encounters another failure, it would compress the remaining time for bring-up and characterization as well as our goal of going through and documenting the entire first iteration. We are mitigating this risk by keeping the design, characterization, and testing planning in parallel so no time is wasted once the hardware is fabricated and functional. This could compensate for the time lost if the next few fab runs also experience failures. 

Upcoming Schedule: 

Despite the fab process restart, we are still in a good position to meet the original timeline and remain on track relative to the buffer that we established in the 2/7 team status report. Once the fab is successfully completed, we must move fast to begin the characterization and measurement process in order to meet our original goal of finishing and documenting the first iteration before spring break. In the meantime, the team, in addition to the characterization and design planning work in parallel, has begun working on the design presentation slides for next week.

Week-Specific Design Impact Considerations.

With regards to this week’s specific design impact considerations questions, part A is written by Jim, part B is written by Charlie, and part C is written by Ethan.

Part A: Our fabbed oscillator and documented, repeatable bring-up workflow improve safety by greatly reducing wiring/probing and trial-and-error during lab testing and measuring. This lowers the likelihood of miswiring, improper loading, and accidental device/equipment damage during power-up and characterization. By providing a repeatable testing infrastructure (defined interfaces, checklists, and measurement access points), we reduce ad-hoc setups and make safe bring-up the default. The workflow also standardizes safe sequencing and measurement steps so new teams can follow a known process instead of improvising on the spot. Overall, it creates a safer and more predictable lab environment while improving the reliability of our measurements.

Part B: Our fabbed oscillator and documented workflow strengthen the HackerFab community as an extended student/instructor group by providing shared infrastructure that teams can organize around. By pairing the design with a repeatable bring-up and measurement workflow, future projects can adopt a common baseline instead of each team developing isolated processes. This improves collaboration across teams and mentors because everyone can align on the same interfaces, expectations, and validation steps. Overall, it supports continuity and collaboration within the HackerFab and ECE community by making our process and lessons learned accessible to future students.

Part C: Our fabbed oscillator and documented workflow improve economic efficiency and saves cost in HackerFab by creating an established, reusable baseline that future teams can use instead of repeatedly spending time and exhausting fabrication resources reinventing basic oscillator bring-up. This benefits not only teams building future oscillators, but also teams building more complex systems that depend on an oscillator (mixed-signal components) as they can start from a validated reference. Through our documentation, we reduce recurring setup/debug labor and increase the likelihood that fabrication runs and lab time yield actionable results. Overall, this also increases the return and availability of shared HackerFab resources (fab slots, equipment time, and staff/TA support) by making downstream projects faster and cheaper to execute.

Team Progress/Schedule

This week, we finalized and delivered our project proposal presentation, aligned on project scope and responsibilities, and confirmed our initial project timeline (Gantt chart). Ethan has already begun fabricating the first template NMOS iteration to enable early bring-up and initial measurements before proceeding into full oscillator iterations.

Our project timeline for the rest of February is as follows. Note that the dates are very conservative and all worst-case/latest projections. We expect to be at or ahead of this schedule if fabrication and bring-up proceed expectedly:

• By February 19 (Latest): Complete fabrication of first template NMOS iteration.

• By February 23: Finish initial bring-up and generate the first characterization curves and measurements on template NMOS using Hackerfab tools.

• By February 28: Complete first-iteration characterization and summarize results to guide the next design/iteration steps. 

 

Risk Mitigation

The main risks, as mentioned in the project proposal presentation, are fabrication or bring-up issues that delay initial measurements as well as measurement limitations (probing/loading effects) that delay clean characterization. We are mitigating this by using a template NMOS first and relying on existing HackerFab tools for the initial characterization phase. Given that we already started the process of doing the first fabrication of the template, if issues arise, we will prioritize a minimal set of essential characterization metrics first and defer non-critical work until after we confirm basic device behavior.

Design/Requirements Changes

No major changes were made to the system requirements, block diagram, or specs this week as we just started the first step. We did clarify the execution plan to start with a template NMOS fabrication + characterization phase before locking later iteration details (including the full demo/test PCB). This reduces risk by validating measurement assumptions early, at the cost of keeping some downstream PCB/demo details provisional until first data is collected. We will mitigate this by continuing PCB planning and SPICE validation in parallel so the design can converge quickly once early measurements are available.