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Team Status Report for 03/27/2021

This week, we have almost finalized all of our project. We are on our track to integrate two weeks later. Michael was able to almost finalize his hardware code to generate all the valid moves. Joseph was able to work on the background subtraction algorithm and will integrate next week. Jee Woong made progress on the board detection, and now we are able to find the coordinates of the pieces.  Next week, Joseph is going to coordinate with what Jee Woong wrote to build a chess system that represents the board state as well as detect moves.

All the team members are on track with the gantt chart. We are on schedule, and with this progress, we might have something to show for next week to be ready for the interim demo.

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Michael’s weekly status report

This week, I worked on synthesizing my custom logic onto FPGA. I had a driver issue that took a while to fix as Intel’s documentation is not the greatest, but everything should run smoothly from now on. I am also continuing to write more verilog code and am getting close to a point at which I can write a simulation testbench and also test on FPGA with its buttons as inputs, or possibly setting a memory mapped register with testbench values. Expect more progress in this direction for next week, and a fully working Game State Logic/Valid moves for 1 Square next week.

I also received a VGA cable from Quinn to help debug anything on the FPGA’s HPS and a quick task I can try next week is to run an unmodified stockfish program on the HPS to verify there will be little problems in its integration. I am still on track to complete Game State Logic/Valid moves for 1 Square as specified in the Gantt chart by next week, which is again 1 week behind our original schedule but I took an extra week to work on HPS/FPGA integration as our original plan had changed. Hopefully that work into integration will save us time when doing a full integration, and hence, I am hopefully still on track.

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Joseph’s Status Report for 03/27/2021

This week I was able to figure out the background subtraction algorithm. Now, I am able to detect the two pieces that were on board. With the feedback to use blob detection, I am also able to find the coordinates of them to later map them to appropriate square that they belong to. That would be the next step, coordinating the pieces to its appropriate squares by creating a chessboard class to map the pieces to. On the pictures, you can see the two pieces that were identified from the background subtraction and also the circles around them that the blob detection was able to find the pieces successfully. I had to change the background to a white background because blob detection only works on a white background.

As for the schedule, I am a little ahead of the initial schedule, but since the integration might take much more time than expected, I might not really be ahead.

Next week, I will be coordinating everything together to make a chessboard system. I will be making chessboard squares, the enumeration for each pieces, and anything else I need to represent the board and the moves.

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Jee Woong’s Status Report for 03/27/2021

For the previous two weeks, I have been working on board-detection to accurately detect every corner of the board. Last week, I tried to use edge detection to retrieve all the edges from the board and then find the rectangular shape of the tiles. Below are the images of my approach for board-detection using edge detection.

As you can see from the image, it looks like it cannot find the squares (tiles) of the board but detect other parts of the board which are irrelevant to board-detection. So, as we decided that we would first detect the corners of the board before the pieces are places, I had to put this approach aside and try with a different approach.

Previously, 49 (7×7) corners could be detected from the function that OpenCV provides. However, I couldn’t detect the entire 81(9×9) corners since the function that OpenCV provides wasn’t able to detect all corners. Since we know that square tiles are separated equally from each square, I calculated the average distance between each of the corners and used the calculated value to predict the rest of the corners. The image below shows the result of the 9×9 corner detections.

(We are using HSV space, but the circles in green will not show clearly on HSV space, so for this report, I converted back to RGB space so that the corners detected are easy to see.)

In addition, I implemented a function that could find the position on the board given an x and y coordinate so that Joseph can use this function in the future to find out which piece has moved and where the piece has moved. So, I believe I have finished the board detection part, although there might be some improvements in the future.

Next week, I will start working on the User Interface part of our project so that once Joseph finishes his computer vision part, we can integrate the User Interface and Computer Vision to test whether they are working correctly.

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Joseph’s Status Report for 03/20/2021

This week I have again tried to use the background subtraction. I seem to keep running into this issue of not having images that are same size. For this reason, the background subtraction algorithm does not run well on the images, and even if I try to break things down, the function absdiff would not take in images with different sizes. As I am going on a flight tomorrow morning to US, I will be working on the real environment when I get back and hopefully not have any of these problems. In specific, I wish to maybe take a video and capture specific frames to background subtract instead of taking individual photos because the photo sizes keep varying for some reason.

As for the schedule, I am not really behind with the initial schedule, but since we realized that we had more work to integrate at the end, we might be a bit behind schedule in terms of work. I hope to get much more done next week as I will have access to the real environment.

Next week, I will be working on tuning the background subtractor, and if it is successful, I will go straight into creating a whole chessboard system on code to integrate everything,

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Team Status Report for 03/13/2021

This week, we all made some progress in each part of our project. Michael had to spend some time on the integration of hardware because of our design change, and he managed to look at some of the documents and try simulations by himself. Joseph and Jee Woong kept working on the Computer Vision part of the project. Joseph started working on detecting moves using the background subtraction algorithm, and Jee Woong made some progress on detecting board corners and coordinates. Joseph is returning to Pittsburgh soon, so this will make Jee Woong easier to collaborate with him and make more progress on the Computer Vision part of the project.

We saw some of the technical comments from the peer feedback forms, and we will try to address more of the technical contents in our design documents which are due this Wednesday. Through our weekly zoom meeting, we are planning to complete the design documents and share our progress.

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Michael’s Status Report for 03/13/2021

This week I worked on continuing HPS (arm core), FPGA integration. I want to fully understand the options for HPS and FPGA before continuing my Verilog implementation so that I know all my options for the full integration. This was a new objective I needed to add for this week so I am slightly behind the schedule now but I am hopeful that I have allotted more than enough time for the Verilog portion of the project.

Specifically this week I have worked through examples from the DE10-standard manual:

https://www.intel.com/content/dam/altera-www/global/en_US/portal/dsn/42/doc-us-dsnbk-42-5505271707235-de10-standard-user-manual-sm.pdf

I worked through some of the examples in chapter 5, 6, 7 and 9, while also reading through a more thorough description of the HPS in another manual:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_54028.pdf

Specifically, I have looked into beginning to understand the integration component of the HPS and FPGA and ensuring now that I have a plan for integration later so that when coding Verilog, I can ensure that the correct registers are loaded with data needed to feed into stockfish.

Although it may seem I am behind on game state logic, I have spent this week preparing part of the integration between stockfish and my custom logic. Ultimately, both will be needed in a complete project and this additional task came up because of a system design change we made after feedback. Hence, my schedule looks ok.

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Jee Woong’s Status Report for 03/13/2021

This week, I worked more on board-detection. Previously, I was working on an image converted into grayscale, and I tried converting a board image into black and white. Because of the lighting issue, when I convert the image into black and white, it wasn’t able to detect the corners of the board. So, Joseph and I decided to keep working on grayscale. The image below is an image when I convert the image to black and white, and as you can see from the image, part of the board gets cut off.

As I mentioned from my previous week’s status report, I had an issue detecting the board when there are pieces placed on the board. So, I tried detecting the edges of the board and find squared so that I can still coordinate corners when there are pieces on the board. When I detect the edges of the board, it also gives out the coordinates of each edge. Thus, I am hoping I can extract the coordinates of the edges of the squares. I am still in the process of working on my new way of board detection. And, I hope this works out well.

Besides, I also have set up the environment to take pictures of the board. Previously, I took pictures with my phone camera, but I can now take pictures with the webcam we bought. And, the result of board detection was the same when I used the new image from the webcam. Next week is the deadline for the board detection, so I will try to finish the board detection with pieces with my own way of detecting squares from the edges.

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Joseph’s Status Report for 03/13/2021

This week I have have looked into getting the coordinates of the corners as well as using the background subtractor. As for the corners, I have found that most of them have values from 0-500, but I realized the values might be pointless without coordinating it with the camera. Hence, I have decided to work on the background subtractor first, see if the camera can recognize the moves, and come back to coordinating the whole steps together. For the background subtractor, I was able to use it on my own webcam on my own video, but I was not able to use it for our purpose, which is comparing two frames to see which coordinates are moving. This was particularly hard for me as  I was working remotely in Korea and did not have access to the chessboard with me to take a video. However, I have requested these to Jeewoong and he was able to take some pictures which I will get working on next week.

As for the schedule, I am on schedule with the initially planned schedule. I might not be next week though because I am switching up some tasks in the future weeks.

Next week, I am going to try to figure out using the background subtractor on two frames and getting to see if it is able to recognize the coordinates of which piece moved correctly. If this is successful, I will get working on detecting the corners correctly so I can get started on the move detection as a whole. There might be more steps than just getting the computer vision to work properly since our team is planning on getting each of tiles set up correctly and the location of pieces set up correctly.  Hence, I want to finish the CV part quickly so I can get started on that.

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Michael’s Status Report for 3/6/2021

This week we worked on finalizing our design and made several changes based on TA/Instructor feedback. As such we will be using hard processor system (HPS) on the FPGA chip as well as an RPi to interface with the HPS. We decided on this because it would ease the integration steps as I will be the only member with access to the FPGA.

As for scheduled tasks, I have set up the Intel default linux distribution onto the FPGA’s HPS and also set up serial communication between the HPS and my computer. This process will be similar to what we imagine our final integration will look like with two programs interfacing with one another via the UART system. Rather than streaming the entire Linux OS output via UART. Basic UART communication between my computer and the FPGA is pictured below.

I have also begun sketching out some of the basic rules and board representations which I will need to consider when generation legal moves via FPGA custom hardware.

https://www.chessprogramming.org/Board_Representation

https://www.chessprogramming.org/Move_Generation

These two link describe the basics which my system verilog implementation must consider. I have also looked over the stockfish open source code to see what slight modifications I will need to make to it to make use of the additions I am planning. Specifically, I should be looking at modifying move generation.

That’s all for this week, next week I will make more progress into working with the HPS and also continue with my system verilog implementation.