This week, I worked on synthesizing my custom logic onto FPGA. I had a driver issue that took a while to fix as Intel’s documentation is not the greatest, but everything should run smoothly from now on. I am also continuing to write more verilog code and am getting close to a point at which I can write a simulation testbench and also test on FPGA with its buttons as inputs, or possibly setting a memory mapped register with testbench values. Expect more progress in this direction for next week, and a fully working Game State Logic/Valid moves for 1 Square next week.
I also received a VGA cable from Quinn to help debug anything on the FPGA’s HPS and a quick task I can try next week is to run an unmodified stockfish program on the HPS to verify there will be little problems in its integration. I am still on track to complete Game State Logic/Valid moves for 1 Square as specified in the Gantt chart by next week, which is again 1 week behind our original schedule but I took an extra week to work on HPS/FPGA integration as our original plan had changed. Hopefully that work into integration will save us time when doing a full integration, and hence, I am hopefully still on track.