This week, I expanded the CPU from BX-only memory addressing to all eight 16-bit ModR/M address combinations, plus direct disp16 addresses. Programs can now use forms such as [BX+SI], [BP+DI+disp], and [SI] for word MOV loads and stores.
I added separate base and index selectors and enables to the decoded instruction record. The decoder now handles each form’s displacement, instruction length, and default segment: BP-based addresses use SS, while the other forms use DS. I extended operand collection so the CPU can retain the base, index, and store data using its existing two register-file read ports. Indexed stores use an additional read step before address generation.
I also integrated Ben’s approved memory and bus interfaces. Both sides now compile against one shared bus-command package, and the integration tests use the current CPU source directly. The tests respect his memory map, including separate RAM, VRAM, ROM, and unmapped regions, along with completion timing and reset cancellation.
The new repeatable make addressing test passed 3,120 memory programs and five subroutine demonstrations, checking 6,400 data-byte transactions. It covers every addressing form and data register, positive and negative displacements, odd addresses, both address wraps, memory waits, and decoder stalls. The same matrix also passed against Ben’s actual memory-controller RTL.
The new subroutine demonstration reads stack parameters through BP, accesses an array through indexed DS addressing, and returns using RET 4. It updates the selected array element and restores BP, BX, SI, and the original stack pointer. All twelve existing CPU regression targets and Ben’s Icarus system suite also passed.
I updated the coverage documentation, diagram guide, and test evidence. Next are byte operands, the remaining decoder and ALU operations, and the I/O and interrupt support needed by the BIOS.