This week, I connected the CPU to the team’s actual BIOS in simulation using Ben’s memory controller and approved memory map. The CPU starts at FFFF:0000 and executes the BIOS reset jump to F000:E000. I added instruction and bus traces, unsupported-instruction diagnostics, timeout detection and VRAM-write logging so failures identify where execution stopped and what the CPU was doing.
I expanded segment support with ES, segment-register transfers, segment PUSH/POP and segment overrides. I also implemented near and far jumps, making sure far jumps update CS and IP together and discard stale prefetched instructions. The decoder now keeps prefixes, displacements, immediates and far-pointer fields separate, preserving them through stalls and clearing them correctly after redirects and reset.
I added byte MOV instructions, byte and word immediate-to-register/memory forms, and accumulator direct-memory transfers. Byte operations preserve the unaffected register byte and use one bus transaction; words use two. The CPU retains operand width, address and data throughout memory waits, and MOV leaves the arithmetic flags unchanged.
Verification passed 2,826 segment/prefix programs and 10,092 MOV programs, alongside 9,214 MOV decoder checks and 21 reset-interruption cases. An assembled diagnostic checked segment initialization and RAM/VRAM accesses across three configurations. Tests covered register aliases, segment overrides, odd addresses, address wrapping and memory stalls. All previous CPU test targets and Ben’s system regressions also passed.
I updated the design, compatibility, toolchain and test documentation, checked the implementation against Ben’s and Govind’s contracts, and recorded unresolved assumptions. The real BIOS currently stops at the unsupported CLI instruction. Remaining work includes ALU and FLAGS support, port I/O, strings and interrupts before the CPU can complete BIOS initialization and boot HELLO.COM.