Category: Ben’s Status Reports

This week, I focused mainly on working on our design report and making sure my portion of the memory and peripheral system was clearly documented. I helped refine the system architecture, memory organization, interfaces, and testing approach so that the report accurately reflects how my subsystem will connect with the CPU and software. I also continued reviewing the RAM, ROM, and address-decoding design to make sure it is consistent with the rest of the system. My progress is on schedule, and next week I plan to return to the RTL implementation and continue integrating the memory subsystem with the CPU interface.

This week, I focused mainly on starting the RTL implementation of the memory subsystem and turning the architecture I had planned over the previous weeks into actual modules. I worked on defining the CPU-to-memory interface with Josh and started implementing the basic RAM, BIOS ROM, and address-decoding logic that will sit between the 8088 and the rest of the system. I also worked through how memory reads and writes should be handled and how the decoder will determine whether a CPU request should go to RAM, ROM, or eventually one of the peripheral interfaces.  I also started setting up simple directed tests for RAM read/write behavior, ROM reads, and address-boundary cases so that each piece can be verified before integrating it with the CPU. This helped clarify some of the timing and interface details that still need to be agreed on between the CPU and memory sides. My progress is currently on schedule, and next week I plan to finish the initial memory modules and tests, connect them more closely to Josh’s CPU interface, and begin working on the next layer of the peripheral system, starting with the I/O decode and storage interface.

This week, I split my time between working on our design presentation slides and continuing to refine the memory subsystem for our project. For the presentation, I helped improve the system architecture, requirements, testing plan, and overall organization of the slides so that the design and interfaces between the CPU, memory, peripherals, and software were clearly explained. On my individual work, I continued working through the CPU-to-memory interface, the initial RAM and BIOS ROM organization, and how address decoding will select between memory and peripheral accesses. I also started outlining the tests I will use for RAM reads and writes, ROM initialization, and address-decode boundaries before integrating with the CPU. My progress is currently on schedule, and next week I plan to finalize the CPU/memory interface with Josh, lock down the first version of the memory map, and begin implementing and testing the RAM, ROM, and address-decode modules before moving further into the storage and peripheral interfaces.

This week, I focused mainly on completing our proposal presentation and getting a better understanding of the memory and peripheral portion of our PC/XT recreation. On my individual portion, I started planning the memory subsystem, including how the BIOS ROM and system RAM will connect to the custom 8088 processor and how address decoding will determine which component responds to a CPU request. I also looked into the peripherals I will be responsible for, including video, keyboard, timer logic, interrupts, and microSD-backed storage, and started thinking through how these pieces will connect to the CPU bus. I began outlining the memory map and the interfaces between the CPU, RAM, ROM, and peripherals so that the different components can be developed independently and integrated later. I also started planning how I will verify the memory system, including RAM read/write tests, ROM initialization checks, and address-decoding tests before integrating it with the CPU. My progress is currently on schedule, and next week I plan to finalize the CPU/memory interface with Josh, define the initial memory map, and begin implementing and testing basic RAM and ROM modules before moving on to the storage and peripheral interfaces.

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