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Jacob’s Status Report for 3/21

Completed controller implementation. Implemented a controller demo that allows the PS to read the PL for the state of the controller and print to uart. Started on the remote syncing protocol implementation that builds upon the existing controller demo to send the controller signals to a remote board through UDP.

I am currently on schedule, and I will finalize the basic control signal syncing next week, ideally completing a demo with two uart sessions monitoring two boards, and pressing buttons on one board will show signals on both sessions.

 

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Team Report 3/14

Project Progress Summary

This week, we have transitioned to our new Arty Z7000 FPGA platform, resolving previous board-specific issues. We have achieved full verification of the 6502 CPU core, and established a high fidelity validation workflow for the PPU. Our progress has moved from individual module logic to physical output. In addition, all team members completed the individual ethics assignment, and had a team discussion on the potential ethical risks in our project concept.

Design Changes

Following our hardware testing in the last few weeks, we have officially moved from the Zedboard to the Arty Z7000 platform. While the core architecture remains the same, this change ensures better compatibility with our target peripherals and simplifies the ROM loader implementation.

Risk & Management

The primary risk is still achieving perfect synchronization between the CPU and PPU modules. We are managing this by using open source tests as golden models for cycle by cycle comparison during integration.

Schedule

The project remains on schedule. We have met our milestones for standalone CPU and PPU verification. Next week, we will begin the phase of full system integration. 

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Michael’s Status Report for 3/14

This week, I have done work on both technical development and the individual ethics assignment. For the ethics assignment, I read all the source materials, answered the questions, and analyzed the trade offs between public health, safety, and welfare for our NES project.

On the hardware side, I have mainly on the VGA-to PPU coordinate mapping. I can display a static test pattern from the pattern table on a physical monitor. Additionally, I worked on the implementation of the XY scrolling logic.

I am currently on schedule, and I will begin drafting the RTL for the visual debug overlay, which will give us debugging toos in the palette data and PPU register states during execution.

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Bert’s status report 3/14

This week I completed verification of the MOS 6502 CPU RTL implementation for all legal instructions. I validated the CPU core using autogenerated test cases to ensure correct functional behavior across the instruction set.

I also finished the architectural design of the PPU, including defining its main functional blocks and how it will interact with the CPU and memory system.

Currently, I am implementing the PPU modules and working on establishing the interface between the CPU and PPU. I am also exploring ways to ensure proper communication and synchronization between the two components.

Next week I will continue implementing and debugging the PPU and focus on integrating it with the CPU to validate their interaction.

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Jacob’s Status Report for 3/14

Acquired and tested the newly arrived Arty Z7-20 boards. Previous issues with the Zedboard are resolved. Validated ROM loader correctness. Validated CPU official opcode correctness with both simulation and hardware. Set up PPU validation workflow with Mesen2 as the golden model. Implemented HDMI video output (not yet connected to the NES core).

I am currently on schedule. Next week, aside from continuing the validation for the PPU, I’ll start to add the controller inputs and the UDP syncing algorithm.

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Michael’s Status Report for 3/7

This week, my efforts focused on moving from internal logic to visual output for the 2C02 PPU. I worked on the sprite rendering pipeline, which now successfully integrates the OAM priority logic with the pattern table fetching mechanism I developed previously. This allows the hardware to correctly handle the transparency and palette selection for up to eight sprites per scanline.

For the upcoming week, I aim to work on the VGA-to-PPU coordinate mapping and demonstrate a static pattern table display on a monitor.

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Bert’s status report 3/7

Finished 6502 CPU core implementation, supports all instructions for MOS 6502. Tested the implementation with autogenerated testcases, remain to work on validating the CPU with official test cases from Klaures. CPU also needs to test for timing issues. Started implementing and debugging PPU implementation. For next week continue to work on PPU and validating CPU implementation

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Jacob’s Status Report for 3/7

Finalized the design and completed the design review. Completed the code for controller input. Ready to pick up the ordered board next Monday and test the ROM loader, AXI-lite interface, and controller inputs.

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Team Report 2/21

Project Progress Summary

This week, we completed the RTL implementation of the Ricoh 2A03 CPU and integrated it into our system testbench. The full instruction set is implemented, and the CPU passes the main assembly test suite, confirming correct baseline functionality.

We also ran additional test sets and found a few edge-case issues that require further debugging. These issues are mainly related to specific instruction behaviors and corner cases. We are currently analyzing waveforms and refining the design to resolve them.

On the multiplayer side, we continued working with the updated architecture where both FPGAs run identical hardware and only synchronize controller inputs. Initial input synchronization tests show consistent behavior under controlled conditions.

We will also complete and submit the final Design Review report based on our presentation and updated implementation details.

Risk Management and Schedule

The main risk remains meeting strict cycle-accurate timing requirements. Now that the CPU RTL is complete, we will begin deeper timing analysis and optimization. Our modular design approach continues to help isolate and manage potential critical paths.

Overall, the project remains on schedule. Next week, we will focus on debugging remaining CPU test failures, continuing PPU development, and further testing the input synchronization system.

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Michael’s Status Report for 2/21

This week, I focused on validating the 2C02 PPU register interface and initiating the next phase of the pixel pipeline. Following our design review presentation on Monday, I worked on the dedicated PPU testbench. I verified that the read/write timing for the internal registers matches the original Ricoh technical specifications, ensuring that the CPU and PPU can communicate without data hazards or missed cycles during the VBlank interval.

On the hardware implementation side, I began writing the system verilog code for the sprite evaluation logic. This involved designing the finite state machine that scans the object attribute memory to identify which of the 64 available sprites should be rendered on a given scanline. I specifically focused on the priority evaluation logic, which ensures that the hardware correctly handles overlapping sprites.

I am currently on schedule. For the upcoming week, I aim to do the following:  keep working on the sprite rendering pipeline, including the logic for fetching pattern table data for sprites and applying palettes. Begin the implementation of the VGA display output module, mapping the internal PPU pixel coordinates to standard VGA timing signals. Incorporate faculty and peer feedback from the design review into the design review report due next Friday.