This week, I focused on validating the 2C02 PPU register interface and initiating the next phase of the pixel pipeline. Following our design review presentation on Monday, I worked on the dedicated PPU testbench. I verified that the read/write timing for the internal registers matches the original Ricoh technical specifications, ensuring that the CPU and PPU can communicate without data hazards or missed cycles during the VBlank interval.
On the hardware implementation side, I began writing the system verilog code for the sprite evaluation logic. This involved designing the finite state machine that scans the object attribute memory to identify which of the 64 available sprites should be rendered on a given scanline. I specifically focused on the priority evaluation logic, which ensures that the hardware correctly handles overlapping sprites.
I am currently on schedule. For the upcoming week, I aim to do the following: keep working on the sprite rendering pipeline, including the logic for fetching pattern table data for sprites and applying palettes. Begin the implementation of the VGA display output module, mapping the internal PPU pixel coordinates to standard VGA timing signals. Incorporate faculty and peer feedback from the design review into the design review report due next Friday.