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Michael’s Status Report for 4/4

The primary focus of this week was the successful execution of our Interim Demo. We have successfully demonstrated both Donkey Kong and Super Mario Bros running on the FPGA hardware in single-player.

I have finalized the PPU scrolling logic to handle both horizontal and vertical mirroring. It allows the hardware to correctly manage nametable transitions. In addition, I conducted stability testing on the Visual Debug Overlay.  By running timing simulations in Vivado, I verified that the overlay logic does not introduce any setup or hold time violations that would interfere with the core NTSC rendering timing.

I am currently on schedule, and we have reached a significant milestone in our project. In the next week, I will collaborate with Jacob to begin testing the UDP synchronization layer by mapping remote controller inputs to the local PPU register interface.

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Bert Status report 4/4

This week, I focused on the architectural refinement and continued validation of the system. I completed a comprehensive refactor of the CPU and PPU codebases to improve modularity and maintainability while ensuring timing stability on the FPGA. Following this refactor, I transitioned to the next phase of APU testing; by identifying and resolving specific logic discrepancies, I successfully passed several additional functional test cases. Looking ahead to next week, I will continue to drive the APU toward full compliance and begin implementing the memory mapper to expand cartridge functionality and overall system compatibility.

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Jacob’s Status Report for 4/4

Demoed the current working CPU+PPU implementation on Monday and Wednesday. Finalized the UDP communication implementation. Tested the implementation with a Raspberry Pi 5 as a mock receiver+sender. Set up the Pi with netem to introduce latency and jitter for future testing. Currently working on integrating the UDP protocol with RTL changes to support control input buffering and frame gating.

I am currently on schedule. I will continue working on the remote multiplayer feature in the upcoming week.

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Team Report 3/28

Project Progress Summary

This week, our team achieved a major milestone: we successfully deployed the integrated CPU and PPU onto the Arty Z7-20 platform and achieved real-time execution of Donkey Kong, with the game rendering correctly on the screen. To reach this, we standardized a new debugging workflow that compares log traces from software emulators against our hardware simulation to quickly resolve behavioral divergences.

On the hardware front, we finalized the NES controller interface. This involved soldering a custom DC voltage regulator to allow the FPGA to safely drive the 5V controller logic and mapping those inputs to the PPU registers. We also integrated sprite-zero hit logic, enabling accurate split-screen scrolling. Finally, the APU is now roughly 50% validated, passing half of its functional test suite.

Significant Risks & Management

The most significant risk currently is the remaining 50% of APU functional tests.  Ensuring cycle-accurate audio timing for triangle and noise channels is complex and could jeopardize the authentic experience use-case. To manage this, we are isolating APU development and using automated test cases to verify individual audio components before full system integration.

Design Changes

We have no new design changes to the system.

Schedule

Our project remains on schedule. With local single-player gameplay now functional on hardware, we are well-positioned for the interim demo. Our focus next week shifts to integrating the UDP network stack for the remote multiplayer component. 

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Michael’s Status Report for 3/28

This week, I focused on hardware integration and synchronizing the rendering pipeline with the CPU core. I worked on integrating the PPU’s sprite-zero hit logic with Bert’s 6502 CPU core. This is a critical timing feature that allows the software to detect when the first sprite, which is typically part of the status bar, is rendered, enabling the split-screen scrolling effects seen in games like Super Mario Bros. 

On the physical hardware side, I soldered a DC voltage regulator  to our NES controller interface. This modification allows the Arty Z7-20 to safely and directly drive the controller’s 5V logic levels from the FPGA’s 3.3V I/O pins. Following this, I collaborated with Jacob to map the controller input states to the specific OAM and PPU registers in the Programmable Logic via the AXI-Lite interface. 

I am currently on schedule, and for the following week, I will finalize the PPU scrolling logic to handle mirroring, which is required for different game cartridges. I will also conduct stability testing on the visual debug overlay to ensure it does not interfere with the main rendering timing during the interim demo. 

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Jacob’s Status Report for 3/28

Established a new testing/debugging workflow, standardizing the log traces of software emulation reference and hardware simulation to catch behavior divergences.

Pushed CPU and PPU correctness further. Successfully synthesized the design and programmed the board. The latest design is able to advance to the game demo after the title screen, matching the behavior of a software emulator.

I am currently on schedule. Next week, aside from the interim demo, I’ll proceed to integrate the UDP button state sending implementation with the current status, and try to integrate the APU if time allows.

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Bert’s Status report 3/28

This week, I focused on the implementation and validation of the APU. I completed a substantial portion of the APU design and successfully passed approximately half of the functional tests, indicating correct behavior for several audio components.

In parallel, I worked on system integration and demonstration. I successfully deployed the current CPU and PPU implementation onto the FPGA platform, achieving real-time execution of Donkey Kong, with the game rendering correctly on screen.

Next week, I will continue refining and completing the APU implementation, with a focus on passing the remaining test cases and ensuring timing accuracy. I will also begin implementing the memory mapper to support more advanced cartridge functionality and improve overall system compatibility.

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Team Report 3/21

Project Progress Summary

This week, our team moved into the integrated testing phase. We hit a major milestone with the completion of the hardware controller interface. Now, our processing system can read real-time button states from the controller. On the rendering side, we have implemented a visual debug overlay that provides a view of palette RAM and internal PPU registers, which is very valuable for debugging the PPU’s MMIO interface. We also initiated the audio processing unit (APU) development.

We also dedicated some effort on the ethics assignment. Beyond the individual assignments, our team met together and had a discussion regarding the worst case scenario for our product. We followed this with a breakout session during the ethics lecture where we engaged in a red teamming exercise.

Significant Risks & Management

The most significant risk at this stage is network jitter and latency within our remote syncing protocol. As we begin sending controller signals via UDP, any inconsistent packet arrival could cause the local and remote game states to diverge. To mitigate this, we are implementing a frame gating logic that will stall the emulated world if required inputs from the network have not arrived. 

Design Changes

We have made no design changes in the past week.

Schedule

Our project remains on schedule. We are now transitioning to verification of full-system synchronization. Our goal for the next few weeks will be a completed one FPGA imlementation of the NES for the interim demo.

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Bert’s Status report 3/21

This week I focused on the RTL implementation of the PPU modules, successfully coding the pattern table fetching logic and the OAM evaluation state machine. I established the memory-mapped I/O interface between the CPU and PPU, ensuring that the 6502 core can correctly access PPU registers within the allocated address space.

I also began researching the functional architecture of the APU, specifically looking into the frame counter and the pulse channel dividers. I have started the initial implementation of the APU’s pulse wave generators and the mixer logic to handle basic digital-to-analog signal summation.

Next week I will continue implementing the remaining APU channels, such as the triangle and noise generators, while focusing on debugging the PPU’s background rendering. I will also work on synchronizing the APU’s timing sequences with the master clock to ensure accurate audio interrupts.

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Michael’s Status Report for 3/21

This week, I focused on the ethics assignment and discussion, and also the development of the visual debug overlay. After we finished our individual ethics assignments, our team gathered together and discussed the ethics questions regarding the worst case scenario of our project. And on Wednesday, I went to the ethics lecture and further discussed the potential ethics problems related to our project.

On the technical side, I drafted and implemented the RTL for the visual debug overlay. The PPU now has a secondary rendering layer that can be toggled to display the current 32-byte palette RAM and key register states. This will be used to verify the XY scrolling logic. I also began assisting with the initial integration of the controller interface to the FPGA.

I am currently on schedule, and for next week, I will focus on integrating the PPU’s sprite-zero hit logic with Bert’s CPU core. I will also solder a DC voltage regulator to the controller to allow the FPGA to directly drive the controller. I will then help Jacob to map the controller to the PPU’s OAM and registers.