This week I focused on the RTL implementation of the PPU modules, successfully coding the pattern table fetching logic and the OAM evaluation state machine. I established the memory-mapped I/O interface between the CPU and PPU, ensuring that the 6502 core can correctly access PPU registers within the allocated address space.
I also began researching the functional architecture of the APU, specifically looking into the frame counter and the pulse channel dividers. I have started the initial implementation of the APU’s pulse wave generators and the mixer logic to handle basic digital-to-analog signal summation.
Next week I will continue implementing the remaining APU channels, such as the triangle and noise generators, while focusing on debugging the PPU’s background rendering. I will also work on synchronizing the APU’s timing sequences with the master clock to ensure accurate audio interrupts.