Author: bshan

This week, I focused on completing final system integration and wrapping up the project. I finalized the memory mapper implementation and successfully integrated it with the rest of the system, ensuring correct interaction across CPU, PPU, and APU components. I validated this integration by testing multiple mapper configurations, including Mapper1 and Mapper2 games, confirming correct functionality and improved compatibility across different cartridges. In parallel, I began drafting the final report, documenting the system architecture, design decisions, and validation results.

As this is the final wrap-up phase, the remaining effort will be dedicated to completing the final report and ensuring all aspects of the system are clearly documented and ready for submission.

This week, I focused on the architectural refinement and continued validation of the system. I completed a comprehensive refactor of the CPU and PPU codebases to improve modularity and maintainability while ensuring timing stability on the FPGA. Following this refactor, I transitioned to the next phase of APU testing; by identifying and resolving specific logic discrepancies, I successfully passed several additional functional test cases. Looking ahead to next week, I will continue to drive the APU toward full compliance and begin implementing the memory mapper to expand cartridge functionality and overall system compatibility.

This week, I focused on the implementation and validation of the APU. I completed a substantial portion of the APU design and successfully passed approximately half of the functional tests, indicating correct behavior for several audio components.

In parallel, I worked on system integration and demonstration. I successfully deployed the current CPU and PPU implementation onto the FPGA platform, achieving real-time execution of Donkey Kong, with the game rendering correctly on screen.

Next week, I will continue refining and completing the APU implementation, with a focus on passing the remaining test cases and ensuring timing accuracy. I will also begin implementing the memory mapper to support more advanced cartridge functionality and improve overall system compatibility.

This week I focused on the RTL implementation of the PPU modules, successfully coding the pattern table fetching logic and the OAM evaluation state machine. I established the memory-mapped I/O interface between the CPU and PPU, ensuring that the 6502 core can correctly access PPU registers within the allocated address space.

I also began researching the functional architecture of the APU, specifically looking into the frame counter and the pulse channel dividers. I have started the initial implementation of the APU’s pulse wave generators and the mixer logic to handle basic digital-to-analog signal summation.

Next week I will continue implementing the remaining APU channels, such as the triangle and noise generators, while focusing on debugging the PPU’s background rendering. I will also work on synchronizing the APU’s timing sequences with the master clock to ensure accurate audio interrupts.

This week I completed verification of the MOS 6502 CPU RTL implementation for all legal instructions. I validated the CPU core using autogenerated test cases to ensure correct functional behavior across the instruction set.

I also finished the architectural design of the PPU, including defining its main functional blocks and how it will interact with the CPU and memory system.

Currently, I am implementing the PPU modules and working on establishing the interface between the CPU and PPU. I am also exploring ways to ensure proper communication and synchronization between the two components.

Next week I will continue implementing and debugging the PPU and focus on integrating it with the CPU to validate their interaction.

Finished 6502 CPU core implementation, supports all instructions for MOS 6502. Tested the implementation with autogenerated testcases, remain to work on validating the CPU with official test cases from Klaures. CPU also needs to test for timing issues. Started implementing and debugging PPU implementation. For next week continue to work on PPU and validating CPU implementation

This week, I completed the full RTL implementation of the Ricoh 2A03 CPU core and successfully integrated it with the VCS testbench environment. The entire instruction set has been implemented and passes the primary assembly test suite, confirming baseline functional correctness. In addition, I verified correct behavior across key subsystems including instruction decode, ALU operations, control flow, and memory interface logic.

However, extended validation across several additional test sets revealed edge-case inconsistencies that require further debugging and refinement. Over the next week, I will focus on resolving these remaining issues, improving coverage across corner cases, and strengthening regression stability to ensure robust and cycle-accurate behavior across all validation scenarios.