This week, I focused on the ethics assignment and discussion, and also the development of the visual debug overlay. After we finished our individual ethics assignments, our team gathered together and discussed the ethics questions regarding the worst case scenario of our project. And on Wednesday, I went to the ethics lecture and further discussed the potential ethics problems related to our project.
On the technical side, I drafted and implemented the RTL for the visual debug overlay. The PPU now has a secondary rendering layer that can be toggled to display the current 32-byte palette RAM and key register states. This will be used to verify the XY scrolling logic. I also began assisting with the initial integration of the controller interface to the FPGA.
I am currently on schedule, and for next week, I will focus on integrating the PPU’s sprite-zero hit logic with Bert’s CPU core. I will also solder a DC voltage regulator to the controller to allow the FPGA to directly drive the controller. I will then help Jacob to map the controller to the PPU’s OAM and registers.