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Daniel’s Status Report for 04/04

This week, I brought up the HPS, HPS-FPGA communication over AXI, and implemented a MIDI state machine in SystemVerilog which can parse a stream of bytes.

These system integration tasks tied together all the work in the synthesizer core that the team has done so far into a platform ready for a polyphonic music demo which could play public domain MIDI tracks that other people have written.

Notably, the MIDI track was from a live input as though it were coming in from a MIDI controller like a keyboard. I was able to stream MIDI from my personal laptop and hear the synthesized output from the speakers. I only used command line tools that came with my system’s default package manager which aligns with the goal of the WaveShaper to be compatible with already existing technologies.

This is a first step in driving the synthesizer modules that we have designed outside of testbench environments. This coming week, the same will be done for the ADSR envelope and the filters in a custom CLI representing the software core.

As you’ve designed, implemented and debugged your project, what new tools or new knowledge did you find it necessary to learn to be able to accomplish these tasks?

I had to learn Quartus II’s Platform Manager and U-Boot.

What learning strategies did you use to acquire this new knowledge?

I usually read documentation, but many of the linked documents provided by Quartus 404’d. I had to filter through old university course labs to try and guess how to write up the IP blocks internally in Quartus correctly.

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Shayaan Status Report 4/4

This week, we successfully synthesized the oscillators on the FPGA. One of the primary issues we encountered involved the DAC logic: although the documentation indicated a two’s complement input, the DAC is wrapped in Intel IP that requires Offset Binary logic. Once we adjusted for this, we were able to produce clean sawtooth, square, and triangle waveforms. We also discovered that the DAC cannot handle a square wave that swings rail-to-rail, as it requires additional headroom to account for higher-order harmonics.

I am still troubleshooting the sine wave generation via a Lookup Table (LUT). I loaded a ROM with a sine .mif file and confirmed that the system is reading the values correctly by verifying them on the Hex display. However, the resulting output is very noisy; while it retains a sinusoidal shape, the source of the noise remains unclear.

Additionally, I synthesized a Chamberlin State Variable Filter (SVF), which features integrated LPF, HPF, and BPF outputs. I have verified the filter’s mathematical correctness through our MATLAB pipeline and completed the SystemVerilog implementation. Despite this, the filter is not yet behaving as expected when running on the FPGA.

Verification is an important step that I take before synthesis on the FPGA and is the reason we have implement a MATLAB pipeline. To use the MATLAB pipeline, I generate a .hex file with our theoretical values. This .hex file in then read in a SystemVerilog testbench and I check after each timestep whether my SystemVerilog output is the same as the hex. This has been very useful in debugging and verifying the filter.