This week, we successfully synthesized the oscillators on the FPGA. One of the primary issues we encountered involved the DAC logic: although the documentation indicated a two’s complement input, the DAC is wrapped in Intel IP that requires Offset Binary logic. Once we adjusted for this, we were able to produce clean sawtooth, square, and triangle waveforms. We also discovered that the DAC cannot handle a square wave that swings rail-to-rail, as it requires additional headroom to account for higher-order harmonics.
I am still troubleshooting the sine wave generation via a Lookup Table (LUT). I loaded a ROM with a sine .mif file and confirmed that the system is reading the values correctly by verifying them on the Hex display. However, the resulting output is very noisy; while it retains a sinusoidal shape, the source of the noise remains unclear.
Additionally, I synthesized a Chamberlin State Variable Filter (SVF), which features integrated LPF, HPF, and BPF outputs. I have verified the filter’s mathematical correctness through our MATLAB pipeline and completed the SystemVerilog implementation. Despite this, the filter is not yet behaving as expected when running on the FPGA.
Verification is an important step that I take before synthesis on the FPGA and is the reason we have implement a MATLAB pipeline. To use the MATLAB pipeline, I generate a .hex file with our theoretical values. This .hex file in then read in a SystemVerilog testbench and I check after each timestep whether my SystemVerilog output is the same as the hex. This has been very useful in debugging and verifying the filter.