• P&P stands for Patt & Patel's Introduction to Computing Systems: From Bits and Gates to C and Beyond
  • (CMU WebISO) P&P Chapter 1 (Fundamentals)
  • (CMU WebISO) P&P Chapter 4 (The von Neumann Model)
  • (CMU WebISO) P&P Appendix A (The LC-3b ISA)
  • (CMU WebISO) P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)
• P&H stands for Patterson & Hennessy's Computer Organization and Design: The Hardware/Software Interface

Required:

• None

Mentioned during lecture:

• Hamming, R. W. (1950). Error Detecting and Error Correcting Codes. Bell System Technical Journal, 29(2).
• Hamming, R. W. (1986). You and Your Research. Transcription of the Bell Communications Research Colloquium Seminar.
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• Amdahl, G. M., Blaauw, G. A., & Brooks, F. P. (1964). Architecture of the IBM system/360. IBM J. Res. Dev., 8(2).
• Rixner, S., Dally, W. J., Kapasi, U. J., Mattson, P., & Owens, J. D. (2000). Memory access scheduling. Proceedings of the 27th annual international symposium on Computer architecture.
• William K. Zuravleff, & Robinson, T. (1997). Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order.
• Patt, Y. (2001). Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE.
• Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.
• Onur Mutlu and Thomas Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007.
• Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda, "Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning", MICRO 2011.
• Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012.
• Onur Mutlu, "Memory Scaling: A Systems Architecture Perspective" Technical talk at MemCon 2013 (MEMCON), Santa Clara, CA, August 2013.

Required:

• Patt, Y. (2001). Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE.
• Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.
• (CMU WebISO) P&P Chapter 1 (Fundamentals)
• P&H Chapters 1 and 2 (Intro, Abstractions, ISA, MIPS)

Mentioned during lecture:

• Moore, G. E. (1965). Cramming More Components onto Integrated Circuits. Electronics, 38(8).
• Burks, A. W., Goldstine, H. H., & Neumann, J. von. (1946). Preliminary discussion of the logical design of an electronic computing instrument.
• Dennis, J. B., & Misunas, D. P. (1975). A preliminary architecture for a basic data-flow processor. Proceedings of the 2nd annual symposium on Computer architecture.
• Gurd, J. R., Kirkham, C. C., & Watson, I. (1985). The Manchester prototype dataflow computer. Commun. ACM, 28(1).
• Kuhn, T. S. (1962). The Structure of Scientific Revolutions.
• (CMU WebISO) P&P Chapter 4 (The von Neumann Model)

Required:

• (CMU WebISO) P&P Chapter 4 (The von Neumann Model)
• (CMU WebISO) P&P Appendix A (The LC-3b ISA)
• (CMU WebISO) P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)