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Labs

Lab 1: Instruction Level ARM Simulator (Due: Fri. 1/24)

Lab 1.5: SystemVerilog Warm-Up (Due: Never)

Lab 2: Single Cycle ARM (Due: Fri. 2/7)

Lab 3: Pipelining (Due: Fri. 2/21)

Lab 4a: Branch Prediction (Due: Fri. 3/21)

Lab 4b: Fine-Grained Multithreading (Due: Fri. 3/21)

Lab 5: Simulating Caches and Branch Prediction (Due: Sun. 4/6)

Lab 6: Memory Hierarchy (Due: Sun. 4/20)

Lab 7: Multicore and Cache Coherence (Due: Fri. 5/2)