This week I worked on creating a MATLAB pipeline for verification purposes. The goal of this pipeline is to emulate the operations performed by the hardware in the FPGA. The pipeline begins with oscillator functions that generate oscillator waveforms over time. These oscillators are then fed into a mixer that combines the waveforms. The mixed signal is subsequently passed through an ADSR envelope. This represents the current state of the pipeline.
The MATLAB implementation is designed to preserve the characteristics of the hardware signals. All function inputs and outputs are represented as unsigned integers, and all values are constrained to fit within 24 bits. In addition to implementing the functions, I created testbenches that plot the resulting output waveforms for analysis.
The next steps are to extend the pipeline by adding filters and audio effects. Once complete, this pipeline will serve as a golden model for formal verification of our RTL implementation.
In addition to the MATLAB work, I spent time debugging the RTL module wave_mixer The main change I made was converting the oscillator outputs from two’s-complement integers to unsigned integers. This simplifies the wave_mixer logic, and the module is now functioning correctly.
It is important that we complete the MATLAB pipeline soon, as our current verification process relies primarily on visual inspection. While it is often intuitive what the expected waveforms should look like, making visual inspection a useful first step, the MATLAB pipeline will allow us to perform verification in a more formal and systematic way.