Accomplished
This week, I met with the Hackerfab members again and joined their session on NMOS Process training and general equipment training. I have also started the process of fabricating the first batch of our test MOSFET to get an initial calibration. So far, I’m certified to use the Hackerfab during daytime over weekdays and I’m trained on all the relevant processes except for the BOE wet etching, which uses HF, and Hackerfab has protocols that prevent undergraduate students from using HF. However, Hackerfab director Jay Kunselman agreed to help me whenever I needed to do BOE wet etching.
Progress/Schedule
I’m on schedule in terms of fabrication, the first batch has already been through the process of doping the polysilicon gate, with a few patterning and doping of the source and drain left to be completed. In our schedule, we are currently still in the phase of calibration and testing the process, so the sooner I can get a few working MOSFETs up, the sooner we can start implementing our design.
Upcoming Deliverables
I expect the first batch of chips (4 of them) to be fully fabbed by the end of next week and wirebond ASAP so Charlie and Jim can start on the measurement, if things go well. Regardless, the latest time for this would be the week after, at which if I still fail to fabricate a MOSFET, then we will need to reconsider our approach. I forgot to take a picture of the chip right now but I’ll do that next week once I patterned the source/drain and have made contact.