Team Progress/Schedule
This week, we finalized and delivered our project proposal presentation, aligned on project scope and responsibilities, and confirmed our initial project timeline (Gantt chart). Ethan has already begun fabricating the first template NMOS iteration to enable early bring-up and initial measurements before proceeding into full oscillator iterations.
Our project timeline for the rest of February is as follows. Note that the dates are very conservative and all worst-case/latest projections. We expect to be at or ahead of this schedule if fabrication and bring-up proceed expectedly:
- By February 19 (Latest): Complete fabrication of first template NMOS iteration.
- By February 23: Finish initial bring-up and generate the first characterization curves and measurements on template NMOS using Hackerfab tools.
- By February 28: Complete first-iteration characterization and summarize results to guide the next design/iteration steps.
Risk Mitigation
The main risks, as mentioned in the project proposal presentation, are fabrication or bring-up issues that delay initial measurements as well as measurement limitations (probing/loading effects) that delay clean characterization. We are mitigating this by using a template NMOS first and relying on existing HackerFab tools for the initial characterization phase. Given that we already started the process of doing the first fabrication of the template, if issues arise, we will prioritize a minimal set of essential characterization metrics first and defer non-critical work until after we confirm basic device behavior.
Design/Requirements Changes
No major changes were made to the system requirements, block diagram, or specs this week as we just started the first step. We did clarify the execution plan to start with a template NMOS fabrication + characterization phase before locking later iteration details (including the full demo/test PCB). This reduces risk by validating measurement assumptions early, at the cost of keeping some downstream PCB/demo details provisional until first data is collected. We will mitigate this by continuing PCB planning and SPICE validation in parallel so the design can converge quickly once early measurements are available.