Author: Hailang Liou

Progress

This week is the last week of work, and has been spent on getting things ready for the final demo.

For the actual synthesizer, I spent this week debugging several issues with the DAC module, did some last minute tuning of effects, and worked on the extra looping feature that we can hopefully have by Monday.

For the DAC, we realized that one of the big sources of noise in our system was incorrect samples coming out of the physical DAC chip, and after many hours of debugging, we realized that the timing of our DAC module on the FPGA may be violating the required setup tim internal to the DAC. Further debugging also revealed that occasionally the sample would change partway through the serial data transmission, leading to completely wrong samples being fed into the DAC. Finally, the very last bug was that we found out that the sine wavetable was missing a sample entry, leading to audible periodic noise. Now there is very little noise audible, which makes me very happy.

For the wavetables, I finished writing a Python script that would transform .wav files into MIF files of the correct format and sample rate to work with our synthesizer. For the complex waveforms, we found a very extensive database of complex wavetables online, and we chose our 4 favorite ones to use in the synthesizer.

For effects, I did some last minute tuning to a lot of the effects, tweaking parameters used in the reverb and unison, as well as adding a phase difference effect in the wavetable blending, which will hopefully improve the blending effect by adding another parameter.

I continued work on the looping module, though I am unsure whether it can be tested and ready by Monday. A lot of my time this week that I had hoped to spend on looping

Finally, I spent a lot of time this week working on the final presentation and poster.

Hopefully everything can be wrapped up in the next day, and we’ll have a good demo. All the noise is gone now, so its just polishing from here on out. I feel pretty good about where we stand now, since my biggest worry was that we couldn’t get rid of the noise and that issue is solved.

Progress

This week was spent mostly on debugging, testing, and preparing for the final in-lab demo and presentation.

For debugging, I worked with the team on integrating all the parts into the final product. The digital side of things is essentially feature complete (with a few extra features thrown in), and work on the digital side has been focused on just small tweaks and polish. Most of the debugging that took place this week was in the analog space, where we have been running into noise issues distorting the final sound quality. Wave-shape distortion issues were fixed when we swapped out the passive speakers we were originally using with powered speakers, and a lot of the noise issue was alleviated with filters in specific points of the analog pipeline. We are currently still working on fixing a ground noise issue.

Testing was done this week of many of the metrics that we set out to meet. For example, I worked on isolating and fixing a bug in the RTL that made the notes slightly flat. Much of the testing was done on the analog attributes, such as testing the filter bands to make sure they were right and testing distortion. Unfortunately, distortion metrics are being affected by the ground noise issue currently so we are still working on fixing that.

I have also begun work on the final presentation and poster, but most of that will be occurring tomorrow.

Scheduling

There isn’t much else to schedule at this point. We mainly want to flesh out the last few bugs from the analog circuitry and make sure everything sounds nice for the public demo day. I might write a few extra features on the digital side in the next week as a fun add-on.

Progress

This week I primarily worked on integration of all the components and modules. I finished the effects chain and worked on dropping it into the pipeline, as well as worked on integrating other miscellaneous components, such as making sure the knob controls worked, as well as finishing the integration of the wavetable wrappers. Most of my time was spent on integration and debugging of the full end-to-end. Time was also spent debugging the implementation and integration of the ADSR and new polyphony modules.

Scheduling

Things are still on track for demo on Monday/Wednesday, the full end-to-end with enhanced polyphony and effects should be ready by then. Next week should be spent mostly on polish as well as presentation readiness.

Progress

This week I worked on several things, namely wavetable controllers and effects tuning.

We realized early this week that because the delay and reverb effects would use too much block RAM on the FPGA that it was no longer viable to make multiple copies of the same wavetable for multiple accesses. At each sample, we need to get a maximum of 8 sample values from the wavetable ROM but the block RAM is only two ported. Therefore, this week, I designed, implemented, and tested wrapper modules for the wavetable that would allow us to access an arbitrary number of wavetable entries at once and get all the data in a fixed delay some cycles later. For the wavetables, I also created modules that would generate simple wave shapes like sawtooth and triangle waves without needing the actual block RAMs.

On the effects end, I finished the design and implementation of the effects chain and have begun tuning. I wrote a Python script that would simulate the reverb module and allow me to quickly iterate through reverb parameter values in software to see what sounded good. I have found a set of parameters that sound good enough for now, although it’s not perfect and I may revisit reverb tuning later. I have also been running comparison tests in both Audacity and MATLAB to get a subjective comparison of what software reverb algorithms.

I have also worked on consolidating segments of the pipeline into a module hierarchy, because I want to try adding a simple recording+looping functionality that would be simple if the correct pieces of the synthesis pipeline are collected in a module that I can black-box and reuse. The main constraint of the recording and looping function is again the availability of block RAM on the device, although with the new wavetable wrappers and the revised reverb design, we should have enough block RAM to spare.

Scheduling

I am satisfied by the progress made this week and believe I am still on track overall for the endgame. My goal this week is to put the whole effects chain on the board and test on real hardware, although part of this is contingent on the analog parts arriving and the amplifier stage being finished.

Progress

Early this week, we had finished integrating the end-to end flow and was able to get sounds playing from keypresses on the keyboard. Later on in the week, I spent some time working on miscellaneous additions to the project that were not detailed in the schedule such as integrating the control knobs into the synthesis pipeline. I also spent a decent amount of time cleaning up the code and removing artifacts from demo-preparation.  I have begun investigating the necessity and implementation of a digital low-pass filter stage before the DAC stage and have played around in MATLAB for filter parameter generation, as well as investigating the digital filter IP cores available for our FPGA. Finally, I resumed work on the effects chain, working on beginning to integrate the effects into the current synthesis chain

Scheduling

I am on track given the revised schedule we developed at the midterm demo. Next week I will work on tuning effects parameters and will begin either working on other parts of the synthesizer or start working on testing. I will need to run more experiments once we have a finished analog filter stage to see whether or not some of the high frequency distortion is caused by the lack of a proper amplifier stage or if the digital filter stage will be necessary. I have a lot of confidence in where we stand as a group after the integration testing we ran last week.

Progress

This week we worked together a lot on preparing for the midterm demo. We worked heavily on integration and testing, and have put together many of the pieces that we had together on hardware. The MIDI interface has been pieced together and completed, fully tested on the FPGA hardware itself. We have been testing by putting successive pieces of the pipeline together, and as of the time of writing this, we have tested the synthesis pipeline up to the decoder and synthesis incrementors, and are working on testing the mixer and the DAC pre-prep modules. We do not anticipate having the effects chain tested on the FPGA board itself for the midterm demo, and have been focusing on the wave blending effects in testing this week. The group as a whole has been working together, so rather than a lot of focus on each of our individual pieces, we have been debugging and testing together.

One issue that has come up this week is the possibility that we may need a digital low-pass filter on-board the FPGA before the DAC due to potential aliasing effects. We will run experiments on the DAC output this week to see if the issue necessitates it, and if it is necessary, I will begin the design of the filter.

Scheduling

The amount of progress we made this week on integration and testing means we will not have to spend as much time later, since the stages of the synthesis pipeline that we have working after this week will not need to be revisited later. My goals for next week are to begin integrating the effects modules and effects chain into the synthesized hardware pipeline. Assuming we can get the basic synthesis pipeline functional early next week, I can begin tuning the effects as well.