Category: Team Status Reports

Progress 

This week was spent on polish and fixing the persistent noise bug from previous weeks. While Charles and Jens worked on moving the analog circuit from the solderless breadboard and soldering all the components onto protoboard, Hailang worked on debugging some DAC issues that was causing missed samples. Overall, this week solved the vast majority of the noise issues in the system. What’s left is just finishing up some soldering and finishing some of the extra features. At this point, we are not looking at any significant risks except for an act of God that ruins our project.

Progress

This week, we finished all of our integration. Our modules have been able to communicate with each other well and we have a sound coming out of our speakers, with all the effects and wave-shapes in place. The sound is a bit noisy, and we have spent most of our past couple of days since the demo trying to fix the issue that we see.  We have solved many noise issues with a combination of a powered speaker and some filters, but some pesky noise remains. We intend to have the issue fixed ASAP, and have begun work on our presentation and poster.

Scheduling

In terms of scheduling, we are a little bit behind because of the bug that we found in our circuit that we have not been able to fix. We are still searching for the cause of the bug and have tried several different solutions to remedy the problem. We hope to have it fixed by tomorrow, but are unsure if we will.

Progress

This week, we finished building all of our necessary modules and are currently working on integrating all of them. We intend to finish integration by tomorrow night and complete tests by the end of next week. This will allow us some time to begin our final report and presentation work.

Scheduling

In terms of scheduling, we are a little bit behind, but have made up for some of the later testing we intended to do by testing our individual modules first before integration. This has sped up the process significantly. Our biggest worry is that we will run into bugs with integration. The analog portion of our design might be difficult to integrate at the end since it is more difficult to debug. Furthermore, the untested nature of some of our modules in the overall pipeline provides some level of concern about completing our full integration.

Progress

This week we continued to finish up the specification feature set and expand from what we had at the midterm demo. Jens is working on expanding the polyphony voices and finishing up the core synthesis pipeline, Hailang has been working on the wavetables and tuning the effects chain, and Charles has been working on adding ADSR envelopes to the synthesis pipeline while he waits for parts to arrive. We anticipate to fully integrate our feature specification next week, as Hailang and Jens will finish the synthesis pipeline and Charles can finish constructing his filters.

Scheduling

The main risk at this point in time is if the analog filter or amplification stages do not perform to specification. We have enough time to compensate and course adjust if issues arise, but it will delay finishing testing until we can isolate the issue and/or find new parts. The parts we use are all designed for audio applications though, so we do not think there will be any major issues there. All that will be left is testing and evaluation according to the metrics we had set.

Progress

This week, we finished up integration and integration testing and completed the end-to-end flow of the synthesizer, such that pressing a key on the keyboard will create sounds on the analog end. Based on preliminary results from our midterm demo product, we are working on a redesign of some parts of the analog filter stage and are also on developing the final amplifier stage to work smoothly with the speaker. On the digital side, we are working on expanding the demo product to include effects and full polyphony, as well as investigating the possibility of needing a digital filter stage.

Scheduling and Risks

We are currently on schedule and do not believe there to be any significant risk ahead. The possibility of needing the final digital filter stage presents some amount of uncertainty, but the main consequence of failing to have the filter ready by the end means some larger amounts of distortion at the very high frequency (highest octave). Fortunately, we believe the difficulty in the filter implementation is low given the filter itself can be configured as an IP core and the filter parameters generated in MATLAB.

Progress

This week as a team we worked on integrating all of our different pieces together to make a full pipeline from the keyboard being pressed until sound is produced. We managed to make two ends work, but as of today are still working on finalizing the last pieces of combining the DAC/Analog and the MIDI/keyboard. As we work for the next day-ish before our midterm demo, we intend to complete the pipeline so that we will at least hear some type of sound at the end of the day tomorrow.

One of the big issues that we are uncertain about is that we may need a digital low pass filter before we send our signal to the DAC to remove higher frequencies from our signal that we do not want to hear. This is currently the biggest risk that we foresee in our near future.

Scheduling

We are currently effectively on schedule, since we have managed to nearly finish integration for our project and once we have a single note that can be played through the pipeline, we should be able to play any given note that we want. This removes a couple weeks at the end of our schedule for integration and gives them to us now, which is why we are effectively on schedule at this point in the semester.

Progress

This week we were all individually tasked with completing the first pass of all of the sections of the pipeline that we were responsible for in preparation for the midterm demo.  This meant that Charles worked on completing the FPGA interface with the DAC and the on board connection layout for this purpose. Hailang was tasked with making sure the UART decode and the MIDI message construction, and the support circuitry for the MIDI signal was ready for the midterm demo, while continuing work on the effects chain.  Jens worked on creating a simplified version of the digital synthesis pipeline. A few key features are being added latter for the purpose of having as functional a midterm demo as possible. The goal for the midterm demo is to have a single note be able to be played through the system from keyboard press to DAC output.  This coming up week is going to be spent finalizing all of the modules for this purpose and connecting them all together for the midterm demo version of the project.

Scheduling

This is slightly behind schedule from where we would have originally liked to have been because we overestimated how much time we would have before the midterm demo for the project.  The schedule has been slightly shifted around to move some portions of the project to after the midterm demo to make sure that the parts that we are aiming to include all work as intended. Many of the features that are to be added after this first iteration of the synthesizer, such as the polyphony, are scaled up versions of the modules that will be included in the midterm demo.  As a result the modules for this pass of the synthesizer will be designed for adaptation to the final version in mind.

Changes to the Design

No significant changes are planned for the design, although we have now planned and expanded the adjustability and the functionality of the effects modules to incorporate some simple expansions we decided would add to the user experience but not increase the workload or complexity by an unreasonable amount.

Risks

Obviously, any design change comes with risks, but we are not worried, since the changes are very minor and the design of our modules allow the additions to be fairly easily integrated. Furthermore, since the additions are not essential to the functionality, they can be scrapped if it needs to be.

Schedule

We are still somewhat behind schedule since all three of us had midterms this week that consumed a lot of our time, as well as travel for spring break. However, we have all planned out work schedules and goals to hit during Spring Break, where we anticipate having plenty of time to work both independently and together if need be. We do not anticipate any necessary changes to the overall schedule.

Changes to the Design

Since there was not too much work done over this week in order to prepare the design review presentation and paper, there are no major design changes either. Professor Mai recommended during the design review presentation that we could utilize the extra block ram to simplify the logic of the effects chain, which is something we had considered to some extent before (extra instances of the wavetable for unison effect calculations). By our rough estimate, we will probably use up a little more than half of the M10K block rams on the Cyclone V, mostly taken up by the delay FIFOs, so we would definitely have the wiggle room for this. One plan for the extra block ram was just to add more waveshapes, since each wavetable only uses up about 2 M10Ks, and it would make the synthesizer cooler to play with without requiring much work. We will further explore utilizing the extra block ram for precomputed effects throughout the next week or two however.

Risks

We do not see any changes to the risk factors from last week, and some of the worries regarding integration have been somewhat alleviated by the creation of the block diagrams for our synthesis and effects pipeline.

Schedule

We are all somewhat behind schedule due to the preparation of the design review presentations and document, but we do not see this as a major issue due to the weeks of built-in slack time within out schedule. There are no changes to the schedule to be made at this time.

Changes to the Design

Last week one of the large changes to the design that we were considering was the implementation of the wavetables in either the SDRAM on the FPGA or in the LUTs of the FPGA.  After design work and deliberation this week we realized that we had neglected to consider a different option of using the block RAM on the FPGA. After running a series of tests to determine how much of this block RAM would be necessary to implement the features that we wish to use memory for we decided that for the board that we are planning to use placing the wavetables in block RAM is the best solution. See Hailang’s weekly report for more details regarding these changes.

Risks

Moving forward a big risk that is becoming apparent is in underestimating the difficulty of the tasks and interfacing between different elements of the project.  For example during the more in depth design process it became clear to us that there would be an issue with interfacing the sample generation component with the effects and DAC because they operated at different clock frequencies.  This was an issue that we had thought about but not on a deep enough level to understand some of the unforeseen issues involved. The two clocks that we had intended to use were a 50 mHz system clock and a 44.1kHz clock for the effects and DAC.  However 50mHz is not evenly divisible by 44.1kHz so this would lead to issues. We believe that this can be dealt with by using the onboard PLLs to generate a system clock that is evenly divisible. However this is just an example of the integration and design consistency risk that we foresee going forward.

Schedule

Currently there have been no modifications to the schedule.