This week I finished the retarget of the beamforming pipeline to the full 20 to 80 kHz band and got every module passing in both the 384 kS/s full-band and 192 kS/s narrow-band configurations. The decimator is now decimation 8 with a 127-tap filter and 128-sample delay buffers. I fixed the 192 kS/s filter coefficients, which turned out to be a 28 to 45 kHz filter, not 36 to 44 kHz, and added a clock enable to the filter so it works with samples that arrive hundreds of clocks apart. The scan controller now steers ±52° in 61 steps and exposes a latched 61 × 32-bit energy snapshot, a sweep counter, a saturation flag and a configurable output shift, which is the interface Essie’s software expects. All four testbenches pass bit-exact or within 1 LSB against the golden model.
I also finished a full pass on the Design Report and re-checked its math against the RTL. I trimmed the longest section toward its page limit.
I am mostly on track. The open item is the integration glue around the verified modules: top level, bus wrapper and bitstream.
For next week:
- Build the top level and register wrapper (including an ID register), and deliver the .bit, .hwh and a written register map to Essie
- Decide the clock structure for the 3.072 MHz mic clock and the 100 MHz logic
- Add the stored-block energy window to the scan controller
- Build the time-shared filter and verify it against the parallel version