Accomplishment
Roshni: Replaced the placeholder straight-line array with the real PCB geometry in the beamforming math, no aliasing issue at our target frequency. Got the fine delay interpolator and scan controller working and verified, with bugs fixed in both. Full 30-channel system passed an end-to-end direction test. Started the next pipeline stage.
Wes: Finished PCB placement/routing, added mounting holes, and submitted the JLCPCB order plus all components. Also wrote up the design-report math for the mic array (SPL, aperture sizing, mic noise, SNR).
Essie: Built scan_limits.py and display_output.py, fixed a heatmap FOV bug, added 19 passing tests, and presented at Wednesday’s design review.
Risks
- Roshni still has an open bug in the decimation stage.
- Clock frequency still isn’t locked in, and that affects a few other pieces (interpolator, decimation, lookup tables), so it needs to happen soon.
- The FPGA-to-software interface is still undefined, but we’re closer now that the RTL side is mostly working.
Design changes
- No changes
Schedule
On track overall. Roshni has one thing to finish next week, Wes is just waiting on parts now, and Essie’s work depends more on teammates’ answers than anything else.
Highlights
Got the full 30-channel system working end to end for the first time — it correctly picked out a known sound direction. PCB design is done and submitted to fab.
Next week
Roshni: find the decimation bug, add full-sweep output to the scan controller, lock the clock frequency, regenerate the lookup tables at full scale. Wes: once the PCB and parts show up, solder everything together in the TechSpark lab and test each mic individually before handing off for RTL bring-up. Essie: get answers on the data interface contract and start swapping in real data, test the DisplayPort-to-HDMI cable on the actual screen.