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Grace’s Status Report for 12/4

Thanksgiving week, Ali and I continued our work on serial communication using UART. We changed our code from using the standard of 1 byte per packet to sending or receiving three packets in a row. Even though we only need to send 16 bits to the FPGA and receive 20 bits, we have to roundup to the next largest byte for padding. Therefore, each time we send or receive, we need three bytes. We were able to make this successfully send and started setting up the code to connect to the DUT that Xiran made.

This past week we continued setting up integration. We also tried a couple of different methods to increase speed and checked to see if using a different laptop would allow us to send at a higher rate. However, unfortunately, we couldn’t seem to go faster. Then we looked into other methods to send our UART protocol and decided to look into using a raspberry pi. We are hoping to setup using the pi this upcoming week.

I also plan to spend time this week working on our final report and video. Additionally, I want to plan out exactly what we show in our demo and poster.

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Team Status Report for 12/4

The biggest concern is still regarding communication, but we are now a bit more concerned about the timing. The fastest baud rate Ali and Grace’s computer can handle is 512,000 bits/second which doesn’t scale for larger instruction quantities. Additionally, the library they are using is relatively slow to read data from the serial cable. They are thinking of switching to using a raspberry pi to handle sending data to the FPGA because it should be able to send data at a faster rate, and it might be easier to use a linux operating system rather than a windows operating system for communication. Ali picked up the Pi on Friday, and has an SD card coming today. She and Grace will be playing around with it later this week to see if they can increase speeds.

Arguably, we’re very happy that UART is basically working — especially compared to all of the issues with Ethernet.

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Ali’s Status Report for 12/4

The most important update from the past 2 weeks is that UART works!! We can successfully send the FPGA 60,000 bytes of data in a row (and it can be sent back correctly!). Grace and I are very close to finishing our end of communication (as in, we need to handle some file I/O to be able to read the test vectors and then write the results from the FPGA to a results file). We’ve planned out this code but haven’t written it yet for 2 main reasons: first, my laptop died when we were writing code and I forgot my charger, second, I’ve been studying for a final on Tuesday. Regardless, we’re very confident that everything will come together pretty easily.

We’ve found out that the maximum baud rate when sending from my computer and Grace’s computer is 512,000 bits/second. This means that for 20,000 instructions, we have roughly 2x speedup, but it’s not very scalable. Additionally, when doing some testing, I found that with the code I’m using to send and receive serial data, it takes a relatively long time to read the data that is sent back to the PC. We have a few ways of addressing this: first, we can try running the sending/receiving portions of the code in different threads. We are also hoping to try using a raspberry pi which can 1) theoretically allow us to send data at a faster rate, and 2) use a different library to send/receive serial data which can reduce some of these latencies.

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Xiran’s Status Report for 12/4

Yay! Last status report!

For the past two weeks, I worked on a few different tasks. During the week of Thanksgiving, I finished our input GUI (below is a screenshot). I also worked on the final presentation slides and practiced delivery, given that I was the presenter for our team this time. This past week, I practiced the presentation more and am beginning to work on integration. More specifically, I need to update the output comparator to accept a slightly different file format that Grace and Ali are working on sending from the FPGA.

I am on schedule. I’m at a point where I’m essentially done with all of my individual tasks for the semester. During this final stretch, I’ll work with my teammates on integration, more testing, plus the final deliverables.

To Tamal and Joel, thank you for your help throughout the semester 🙂 See you at our demo!

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Grace’s Status Report for 11/20

This past week Ali and I researched more about serial communication and clock crossing protocols, as well as started implementing our own protocol. We started by using the structure given in the 18-240 serial lab and set up the receiving end of the protocol. Some of the week was spent debugging the receiving end using the sending protocol testbenches in the 240 lab (its in the 240 afs space under lab 5 if you want to see what it does). Once we felt that our receiving protocol was sturdy enough, we moved on to the transmitting protocol, which does the receiving protocol in reverse.

Given that our FPGA clock speed is much faster than the baud rate for serial communication, we decided to set the speed to 1/10th of the FPGA rate. This way, when performing clock crossing, we only have to wait for or hold values for 10 cycles, depending on sending/receiving.

We also spent time this week playing around with PuTTY. Connecting to the board using our laptops is relatively easy and we can send bytes directly by typing them into the terminal. Now, we need to create a program that can read data from a file and send it across using PuTTY.

In this next week, we will finish creating the transmitting SystemVerilog code, look into creating a program to send/receive on PuTTY, and work on the final presentation slides.

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Team Status Report for 11/20

The most significant risk in our project remains to be the communication protocol. After deciding to switch from using Ethernet to UART, Ali and Grace made good progress on implementing UART this week. The receive direction of the datapath is completed, while the transmit direction is in progress. This upcoming week, Ali and Grace will work on transmit, after which we will have a functional protocol, making our system flow complete.

Meanwhile, Xiran has been working on the GUI. The output GUI is complete, and she will work on the input GUI this coming week.

There have been no changes to our existing design or schedule.

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Xiran’s Status Report for 11/20

This past week, I finished implementing our output GUI. Below is a gif demonstrating the interface:

The user can upload the two output files (golden and actual) and see 1) graphed statistics about the test case and 2) which instruction, if any, failed plus the register dump comparison. We present these information in order to help the verification engineer better understand the tests being run and more quickly isolate bugs.

I am on schedule. Next week, I plan to implement the input GUI, which should be simpler since it involves less components, and also work on the final presentation slides. There are improvements I want to make to this output GUI (play around with layout and colors); I will come back to this at the end of the semester.

Happy early Thanksgiving!

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Ali’s Status Report for 11/20

I think Grace and I made a lot of progress this week. We also worked together on everything so it might sound redundant. Anyways, we modified the receive datapath, so that it works for our use case (removed error handling and enabled the data to be sampled). We also explored how to send data to the FPGA via serial communication, so we installed puTTY (a windows communication handler), and successfully sent data down the serial cable (we knew this because we saw the RX light flash). We also began implementing the transmit portion of serial communication. I’m hoping to work on the transmit datapath tomorrow.

This upcoming week, we will finish transmit, make a demo, and then deal with clock crossing (between the serial module and the DUT). We also need to solidify the script we’re using to send data from the PC to the FPGA. I think we will be able to get serial working, and it’ll be okay.

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Xiran’s Status Report for 11/13

This past week, I researched frameworks to use to improve our UI and began working on the output GUI.

For the first half of the week, I planned to make a python GUI that runs on the ece machines, but after I ran into many issues, I decided to make a web app instead. The first issue was that the library choices I have are quite limited (most libraries aren’t installed on these machines, and I don’t have permission to install anything). After I settled on Tkinter and Matplotlib, two libraries that are already installed, I ran into package dependency issues and bugs that have been fixed in newer releases, but not in the old release on those machines.

Getting even a simple plot to show proved to be difficult, so my plan switched to making a web app instead in the second half of the week. However, given that I do not have web app experiences, I want to use a web app builder to simplify the process. I discovered a web app builder called anvil, that allows me to make a UI by dragging and dropping components and code client and server side code in Python. I’ve since been playing around with this framework, and here’s what I’ve been able to get to work so far:

This is showing that the user can upload a test case file and get some graphed statistics about that test case.

I am on schedule. Next week, I will continue building this GUI. The goal is for the user to be able to upload relevant files and see more statistics about the test case as well as a failure analysis (what instruction, if any, failed, plus a table comparing the expected vs actual register dumps).

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Team Status Report for 11/13

Right now our biggest risk remains the communication protocol. Given the challenges we have experienced with using Ethernet, we have decided to switch gears from Ethernet to serial communication using UART. This will come with a performance drop, but it gives us much better chances of actually having a working product. This past week, Grace and Ali implemented half of the UART protocol and tested in simulation. They will continue implementing the protocol this upcoming week, with the goal of having a working protocol on the FPGA by Thanksgiving break.

Meanwhile, Xiran has begun working on the output GUI. We also have a new schedule made for the demos this past week, attached below for reference. Until Thanksgiving break, Grace and Ali will work on UART, while Xiran will work on the GUI. We will integrate and work on the report after.