This past week Ali and I researched more about serial communication and clock crossing protocols, as well as started implementing our own protocol. We started by using the structure given in the 18-240 serial lab and set up the receiving end of the protocol. Some of the week was spent debugging the receiving end using the sending protocol testbenches in the 240 lab (its in the 240 afs space under lab 5 if you want to see what it does). Once we felt that our receiving protocol was sturdy enough, we moved on to the transmitting protocol, which does the receiving protocol in reverse.
Given that our FPGA clock speed is much faster than the baud rate for serial communication, we decided to set the speed to 1/10th of the FPGA rate. This way, when performing clock crossing, we only have to wait for or hold values for 10 cycles, depending on sending/receiving.
We also spent time this week playing around with PuTTY. Connecting to the board using our laptops is relatively easy and we can send bytes directly by typing them into the terminal. Now, we need to create a program that can read data from a file and send it across using PuTTY.
In this next week, we will finish creating the transmitting SystemVerilog code, look into creating a program to send/receive on PuTTY, and work on the final presentation slides.