I think Grace and I made a lot of progress this week. We also worked together on everything so it might sound redundant. Anyways, we modified the receive datapath, so that it works for our use case (removed error handling and enabled the data to be sampled). We also explored how to send data to the FPGA via serial communication, so we installed puTTY (a windows communication handler), and successfully sent data down the serial cable (we knew this because we saw the RX light flash). We also began implementing the transmit portion of serial communication. I’m hoping to work on the transmit datapath tomorrow.
This upcoming week, we will finish transmit, make a demo, and then deal with clock crossing (between the serial module and the DUT). We also need to solidify the script we’re using to send data from the PC to the FPGA. I think we will be able to get serial working, and it’ll be okay.